Chip Package Structure With Stacked Through-Holes For Heat Dissipation
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Solution Overview
Problem
The existing chip packaging process for light emitting chips faces challenges in heat dissipation and throughput, necessitating an improved package structure and method for enhanced performance.
Innovation Solution
A package structure for chips is developed, featuring a carrier substrate with stacked through-holes and conducting layers that electrically connect electrodes, allowing for efficient heat dissipation and improved connectivity, along with a method that includes forming through-substrate vias and conducting layers to connect the chip to external electrical elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a traditional bonding process is used to package light emitting chips, then the chip can be connected to the printed circuit board, but heat dissipation and throughput are insufficient
Solution Approach 1:
The patent divides the through-hole into multiple stacked segments (first through-hole portion, second through-hole portion, third through-hole portion) that penetrate different layers of the carrier substrate. Each segment can be independently formed and filled with conducting material, allowing for optimized thermal and electrical pathways while maintaining manufacturing feasibility. This segmentation resolves the contradiction by enabling improved heat dissipation through multiple thermal paths without requiring a single complex through-hole structure that would reduce productivity.
Solution Approach 2:
The patent transitions from a traditional planar bonding structure to a three-dimensional stacked through-hole structure. The stacked holes extend vertically through multiple layers of the carrier substrate, creating additional dimensional pathways for heat dissipation and electrical connection. This dimensional change enables simultaneous improvement in heat dissipation (through vertical thermal paths) and throughput (through parallel connection paths) without compromising the traditional bonding process.
2Reliability
If stacked through-holes with conducting layers are formed, then heat dissipation and electrical connection are improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent performs preliminary actions by pre-forming the stacked through-hole portions and pre-depositing conducting layers on the sidewalls before final chip assembly. The conducting layers are formed on the sidewalls of each through-hole segment in advance, creating ready-made electrical pathways. This preliminary preparation simplifies the overall manufacturing process by separating the complex through-hole formation and conducting layer deposition from the chip bonding step, thereby improving electrical connection reliability without proportionally increasing overall process complexity.
Solution Approach 2:
The patent employs a nested structure where multiple through-hole portions are stacked within each other, with each hole segment containing conducting material. The first through-hole portion is nested within the carrier substrate, the second through-hole portion is nested within and aligned with the first, and the third through-hole portion is nested within and aligned with the second. This nested arrangement consolidates multiple electrical and thermal pathways into a compact vertical structure, improving reliability while containing the manufacturing complexity within a organized hierarchical framework.
Data Source
AI summary
An embodiment of the invention provides a package structure for chip. The package structure for chip includes: a carrier substrate having an upper surface and an opposite lower surface; a chip overlying the carrier substrate and having a first surface and an opposite second surface facing the upper surface, wherein the chip includes a first electrode and a second electrode; a first conducting structure overlying the carrier substrate and electrically connecting the first electrode; a second conducting structure overlying the carrier substrate and electrically connecting the second electrode; a first through-hole penetrating the upper surface and the lower surface of the carrier substrate and disposed next to the chip without overlapping the chip; a first conducting layer overlying a sidewall of the first through-hole and electrically connecting the first conducting electrode; and a third conducting structure overlying the carrier substrate and electrically connecting the second conducting structure.