Chip Package Vertical Stacking Reduces Conductive Bump Density
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Solution Overview
Problem
As electronic devices trend towards being lighter, thinner, and smaller, multi-chip package structures face challenges in efficiently disposing conductive bumps in limited spaces, particularly with increasing semiconductor chip density.
Innovation Solution
A chip package structure is developed, comprising a first semiconductor substrate with a second substrate bonded on top, featuring a lower semiconductor layer electrically contacting pads, a conducting layer on the upper semiconductor layer, and a signal conducting structure on the lower surface, which reduces conductive bump density through strategic layering and bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-chip package structures are used to increase device density, then functionality and performance are improved, but conductive bump density increases and space becomes limited
Solution Approach 1:
The patent transitions from a conventional planar arrangement of conductive bumps to a three-dimensional stacked configuration. Multiple semiconductor chips are bonded vertically across different substrates (first substrate, second substrate, third substrate), utilizing the vertical dimension to accommodate multiple functional chips without increasing the horizontal footprint. This dimensional transition allows high-density integration while maintaining manageable conductive bump density at each bonding interface.
2Adaptability or versatility
If more semiconductor chips are integrated in a single package, then device functionality increases, but the package size and complexity increase
Solution Approach 1:
The patent divides the multi-chip package into distinct functional modules, each comprising a semiconductor chip mounted on a dedicated substrate (first substrate for logic chip, second substrate for MEMS chip, third substrate for sensor chip). Each module can be independently designed, fabricated, and tested before final assembly. This segmentation reduces overall package complexity by modularizing the integration process and allowing parallel development of different chip functions.
Solution Approach 2:
The patent introduces intermediate substrates (first substrate, second substrate, third substrate) that act as mediators between the semiconductor chips and the external environment. These substrates provide standardized bonding interfaces, signal routing layers, and mechanical support, simplifying the integration of multiple diverse chips. The substrates serve as intermediary platforms that manage the complexity of inter-chip connections and external package interfaces.
3Area of stationary object
If conductive bumps are densely disposed to accommodate high chip density, then space utilization improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the conductive bump connections into multiple separate bonding interfaces across different substrates rather than requiring all connections at a single interface. Each substrate-chip interface has its own set of conductive bumps, distributing the precision requirements across multiple manageable bonding operations. This segmentation allows each bonding step to use moderate bump density with achievable precision, avoiding the need for extremely high precision in a single dense interface.
Data Source
AI summary
An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.