Chip Package Stacking with Redistribution Layers and Molding
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Solution Overview
Problem
The miniaturization of electronic products is hindered by the challenge of shielding the sensing surface of chips with sensing devices, making it difficult to further reduce the size of chip packages and circuit boards using existing system-in-package (SiP) technology.
Innovation Solution
A chip package design that includes a first redistribution layer, a bonding structure, a molding layer, and a second redistribution layer, allowing for the stacking of chips with sensing regions and conductive pads, where the second chip is electrically connected to the first chip through the redistribution layers and bonding structures, eliminating the need for through-silicon via technology and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If system-in-package (SiP) technology is used to reduce chip package size, then the dimensions of chip packages are reduced, but the sensing surface of chips with sensing devices cannot be shielded
Solution Approach 1:
The chip package is divided into distinct functional regions: a sensing region with exposed sensing surfaces for detecting external stimuli, and a non-sensing region containing conductive pads and bonding structures for electrical connections. This segmentation allows the sensing surface to remain accessible while other components are packaged and protected.
Solution Approach 2:
Different regions of the chip are treated differently: the sensing region maintains an exposed surface for environmental interaction, while the non-sensing region is encapsulated with molding compound for protection. The bonding structure is selectively positioned to connect only the non-sensing region to external circuits, preserving sensing functionality while providing package-level protection where needed.
2Reliability
If chips are individually disposed on circuit board with indirect electrical connection, then electrical connection paths are provided, but the size of circuit board and finished electronic product cannot be reduced further
Solution Approach 1:
Multiple functional elements are merged into a single integrated chip package structure: the sensing chip, conductive pads, bonding structures, and molding compound are combined into one unified component that can be directly mounted on the circuit board, eliminating the need for separate connection elements and reducing overall size.
Solution Approach 2:
The package structure utilizes three-dimensional stacking and vertical arrangement of components. The bonding structure extends vertically from the chip surface to the circuit board, and the molding compound provides three-dimensional encapsulation, allowing efficient use of vertical space rather than spreading components horizontally across the circuit board.
3Strength
If molding layer is formed to cover redistribution layer and surround first chip, then structural strength and reliability are enhanced, but manufacturing process complexity increases
Solution Approach 1:
The molding compound is applied in a preliminary encapsulation step that simultaneously protects multiple components (chip, bonding structure, and exposed conductive pads) and establishes the final package geometry. This preliminary molding action simplifies subsequent manufacturing steps by pre-positioning and protecting critical elements before final assembly operations.
Data Source
AI summary
A chip package is provided. A first bonding structure is disposed on a first redistribution layer (RDL). A first chip includes a sensing region and a conductive pad that are adjacent to an active surface. The first chip is bonded onto the first RDL through the first bonding structure. The first bonding structure is disposed between the conductive pad and the first RDL. A molding layer covers the first RDL and surrounds the first chip. A second RDL is disposed on the molding layer and the first chip and is electrically connected to the first RDL. A second chip is stacked on a non-active surface of the first chip and is electrically connected to the first chip through the second RDL, the first RDL, and the first bonding structure. A method of forming the chip package is also provided.