Chip Package Channel Stiffener Frame Warpage Reduction
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Solution Overview
Problem
Conventional semiconductor chip packaging substrates tend to warp due to mismatches in coefficients of thermal expansion, which complicates the reduction of electrical pathways needed to lower power supply inductance and improve power fidelity.
Innovation Solution
A channel stiffener frame is coupled to the substrate, featuring spaced apart opposing walls defining a channel with a central opening, providing stiffening while accommodating passive devices and reducing warpage, and a lid is secured to the frame to cover the semiconductor chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the substrate is made thinner to reduce electrical pathways, then power supply inductance is reduced and power fidelity is improved, but substrate warping increases due to thermal expansion mismatches
Solution Approach 1:
The substrate is divided into multiple layers (core layer, first build-up layer, second build-up layer) with different functions. The core layer provides structural support and stiffness to prevent warping, while the build-up layers contain the electrical pathways and interconnects. This segmentation allows the substrate to be thin enough for low inductance while maintaining planarity through the supportive core layer.
Solution Approach 2:
The substrate uses composite materials with different properties in different layers. The core layer uses glass-filled epoxy for high stiffness and dimensional stability, while the build-up layers use resin materials for electrical insulation and pathway formation. This composite structure enables the substrate to achieve both thinness for low inductance and sufficient rigidity to prevent warping.
2Reliability
If the substrate is made thinner to improve power transfer, then power fidelity is improved, but resistance to warpage decreases
Solution Approach 1:
The substrate structure is segmented into a thin build-up layer containing electrical pathways and a thicker core layer providing mechanical strength. This allows the overall substrate to be thin for good power transfer fidelity while the core layer maintains warpage resistance.
Solution Approach 2:
Different regions of the substrate have different thicknesses and material properties. The core layer provides localized structural support and warpage resistance, while the build-up layers are optimized for electrical performance with thinner profiles to reduce inductance and improve power transfer fidelity.
3Use of energy by moving object
If electrical pathways are shortened to reduce inductance, then power supply inductance is reduced, but substrate warping increases
Solution Approach 1:
The substrate is segmented into functional layers where the build-up layers contain shortened electrical pathways for low inductance, while the core layer provides the structural integrity needed to maintain planarity. This segmentation decouples the electrical performance requirements from the mechanical stability requirements.
Data Source
AI summary
Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.