Chip Package Stress Buffer Layer Thermal Expansion Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing chip package structures either fail to effectively protect chip edges or suffer from reliability issues due to differences in thermal expansion coefficients between the encapsulant and the chip, leading to decreased product service life.
Innovation Solution
A chip package structure that includes a stress buffer layer covering the active and peripheral surfaces of the chip, combined with insulating layers and solder balls, enhances mechanical strength and reliability by providing direct protection to chip edges and aligning thermal expansion coefficients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If resilient material or packaging material is used to protect chip edges, then mechanical strength is improved, but thermal expansion mismatch causes reliability degradation
Solution Approach 1:
The patent changes the material parameter of the protection layer by using an organic-inorganic composite material (such as silane-modified polymer) that has been specifically designed to match the thermal expansion coefficient of the chip. This material parameter change resolves the thermal expansion mismatch problem while maintaining mechanical strength.
Solution Approach 2:
The patent employs composite materials combining organic and inorganic components (e.g., silane-modified polymers) to achieve both mechanical strength and thermal expansion compatibility. The composite structure allows simultaneous optimization of protective properties and thermal matching with the chip substrate.
2Ease of manufacture
If conventional encapsulant is used, then manufacturing is simple, but chip edges are not effectively protected
Solution Approach 1:
The patent uses organic-inorganic composite materials (such as silane-modified polymers) that can be applied using conventional encapsulation processes while providing superior chip edge protection. The composite material maintains ease of manufacture through existing coating and curing techniques while significantly enhancing protective properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively protects chip edges and enhances overall structural reliability by using a stress buffer layer and insulating layers to align thermal expansion coefficients, thereby improving the chip package's mechanical strength and service life.
Implementation Method 1
a difference in thermal expansion coefficient between the encapsulant and the chip may lead to a decrease in the reliability and product service life
Data Source
AI summary
A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.