Chip Package With Substrate Openings Eliminates Bonding Wires

Solution Overview

Problem

Multi-chip package structures face challenges in reducing size and increasing fabrication costs due to the need for extensive bonding wires, which is not suitable for portable electronic products.

Innovation Solution

A chip package structure is developed using a first substrate with a second substrate having openings that define conducting regions, a carrier substrate, and insulating and conducting layers to facilitate electrical connections without the need for extensive bonding wires, allowing for a more compact and cost-effective packaging solution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multi-chip package structures use bonding wires to connect chips, then electrical connections between chips are achieved, but the package size increases and fabrication cost increases

Engineering Contradiction:

Improveelectrical connectionVSAvoidpackage size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts and eliminates the bonding wire component from the package structure. Instead of using separate bonding wires to connect chips, the invention integrates electrical connection functions directly into the substrate through conducting regions and openings, removing the need for extensive bonding wires and thereby reducing package size.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the electrical connection function with the substrate structure itself. The substrate is designed with integrated conducting regions, openings, and insulating layers that simultaneously provide mechanical support and electrical connectivity, eliminating the need for separate bonding wire components.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If multi-chip package structures use bonding wires to connect chips, then electrical connections between chips are achieved, but fabrication cost increases

Engineering Contradiction:

Improveelectrical connectionVSAvoidfabrication cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the electrical connection function with the substrate structure itself. The substrate is designed with integrated conducting regions, openings, and insulating layers that simultaneously provide mechanical support and electrical connectivity, eliminating the need for separate bonding wire components and reducing fabrication complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The substrate serves multiple functions simultaneously: it provides mechanical support for the chips, establishes electrical connections through integrated conducting regions, and provides insulation through insulating layers. This multi-functionality reduces the number of separate components needed and simplifies the manufacturing process.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If traditional packaging structures are used, then chip integration is achieved, but packaging efficiency is reduced due to excessive package size

Engineering Contradiction:

Improvepackaging efficiencyVSAvoidpackage size

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent extracts and eliminates the bonding wire component from the package structure. Instead of using separate bonding wires to connect chips, the invention integrates electrical connection functions directly into the substrate through conducting regions and openings, removing the need for extensive bonding wires and thereby reducing package size.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from a planar bonding wire connection approach to a vertical integration approach using substrate openings and conducting regions. The electrical connections are established through the thickness of the substrate rather than through lateral wire routing, enabling more compact packaging.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9035456B2Chip package and method for forming the same

Publication Date: 2015.05.19 XINTEC INC

AI summary

An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate has at least one opening penetrating through the second substrate, and the at least one opening defines a plurality of conducting regions electrically insulated from each other in the second substrate; a first insulating layer disposed on a side of the first substrate and filling in the at least one opening of the second substrate; a carrier substrate disposed on the second substrate; a second insulating layer disposed on a surface and a sidewall of the carrier substrate; and a conducting layer disposed on the second insulating layer on the carrier substrate and electrically contacting with one of the conducting regions.