Chip Package Substrate Pad Segmentation for Bonding Overflow Control
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Solution Overview
Problem
In conventional chip packages, the surface bonding layer on second substrate pads often exceeds the contact surface area of bumps, leading to material overflow and contamination of the chip during thermal compression bonding, as the contact surface area of bumps is not fully utilized, resulting in incomplete bonding and potential chip contamination.
Innovation Solution
A method is introduced where a solder mask layer is used to pattern and expose only the necessary areas of second substrate pads for the surface bonding layer, ensuring that the bonding layer does not overflow and contaminates the chip, by forming the surface bonding layer within openings created by the solder mask, allowing for proper thermal compression bonding without excess material spreading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the surface bonding layer is formed to completely cover the second substrate pads, then the bonding area is increased, but the bonding layer material overflows and contaminates the chip during thermal compression bonding
Solution Approach 1:
The second substrate pad is divided into two distinct regions: a first region covered by the surface bonding layer for bonding purposes, and a second region exposed without bonding layer coverage. This segmentation allows the bonding layer to provide adequate bonding area while preventing overflow and contamination of the chip during thermal compression bonding.
Solution Approach 2:
The surface bonding layer is applied selectively to specific regions of the second substrate pad rather than uniformly across the entire pad surface. The first region receives the bonding layer for effective bonding, while the second region remains exposed to prevent contamination, achieving local optimization of bonding performance and contamination prevention.
2Strength
If the surface bonding layer completely covers the second substrate pads, then the bonding strength is improved, but the material is not fully utilized and overflows during bonding
Solution Approach 1:
The second substrate pad is segmented into a first region with bonding layer coverage for bonding and a second region without coverage. This ensures the bonding layer material is concentrated where needed for bonding strength while preventing overflow and material waste during the bonding process.
Solution Approach 2:
Instead of applying the bonding layer excessively across the entire second substrate pad surface, the bonding layer is applied partially only to the first region where bonding is required. This partial action achieves sufficient bonding strength while avoiding material overflow and waste.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures complete and clean bonding between chip pads and substrate pads, preventing surface bonding layer overflow and maintaining chip cleanliness, thereby enhancing the reliability and performance of the chip package by ensuring all material is utilized effectively during the bonding process.
Implementation Method 1
The conventional chip package 100 is formed by a thermal compression bonding process. In particular, after the bumps 130 are respectively formed on the chip pads 112 in advance, and the surface bonding layer 126 is formed on the first substrate pads 122 and the second substrate pads 124, each of the bumps 130 is then pressed onto one of the first substrate pads 122 or of the second substrate pads 124 by means of high-temperature compression. Each of the bumps 130 chemically reacts with the surface bonding layer 126 to form the interface metal layer 140
Implementation Method 2
Each of the bumps 130 chemically reacts with the surface bonding layer 126 to form the interface metal layer 140, so that the chip 110 is electrically connected to the package substrate 120
Data Source
AI summary
A chip package including a chip, a package substrate, and a plurality of bumps is provided. The chip has a plurality of chip pads disposed on a surface of the chip. The package substrate has a plurality of first substrate pads, a plurality of second substrate pads, and a surface bonding layer. The first substrate pads and second substrate pads are disposed on a surface of the package substrate. The surface bonding layer is disposed on the first substrate pads and second substrate pads, and covers a part of each second substrate pad. The bumps are respectively disposed between the chip pads and the surface bonding layer. The chip is electrically connected to the package substrate through the bumps. Each first substrate pad is electrically connected to one of the bumps, and each second substrate pad is electrically connected to at least two of the bumps.