Multi-chip Package Heat Dissipation Substrate
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Solution Overview
Problem
High heat dissipation challenges in chips due to hot spots result in increased spreading resistance, affecting performance and reducing the service life of chips.
Innovation Solution
A chip packaging structure that includes a heat dissipation substrate, a pre-molded chipset with thermally conductive substrate and multiple smaller-sized chips electrically connected by a patterned circuit, encapsulated with a first and second encapsulant, and connected to the heat dissipation substrate via an interconnection, reducing spreading resistance and enhancing heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single chip architecture is used, then the device complexity is reduced, but the heat concentration problem increases and spreading resistance increases
Solution Approach 1:
The patent divides a single large chip into multiple smaller chips (first chip, second chip, third chip, fourth chip) arranged in a 2x2 matrix on the substrate. This segmentation distributes the heat generation across multiple smaller units rather than concentrating it in one large chip, thereby reducing heat concentration and spreading resistance while maintaining the required functional complexity through inter-chip connections via through-substrate vias.
2Device complexity
If a single chip architecture is used, then the device complexity is reduced, but the spreading resistance increases
Solution Approach 1:
The patent segments the chip into four smaller chips arranged in a matrix, which distributes the heat load across multiple thermal pathways to the substrate. This segmentation reduces the spreading resistance by creating multiple parallel heat dissipation paths, improving reliability without significantly increasing device complexity as the chips are interconnected through standardized via structures.
Solution Approach 2:
The patent combines multiple smaller chips into a unified multi-chip module that functions as a single integrated unit. The chips are closely spaced and interconnected through through-substrate vias, merging their electrical and thermal functions while distributing the heat load, thereby reducing spreading resistance and improving reliability compared to a single large chip.
3Temperature
If multiple smaller chips are used instead of a single chip, then heat dissipation is improved and spreading resistance is reduced, but the total cost increases
Solution Approach 1:
The patent segments the chip into four smaller chips, which improves heat dissipation by distributing heat across multiple units. The cost increase is mitigated by using a cost-effective substrate material (such as aluminum or copper) and implementing efficient inter-chip connections through through-substrate vias, which reduce the need for expensive packaging and interconnection structures.
Solution Approach 2:
The patent changes the physical parameters of the chip architecture by dividing it into multiple smaller units with different spatial arrangements. This parameter change allows for optimized heat dissipation paths and enables the use of cost-effective materials and manufacturing processes for the substrate and interconnections, balancing the cost increase with improved thermal performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces spreading resistance, improves heat dissipation, and extends the service life of chips while lowering the total cost of the packaging structure by distributing heat evenly and maintaining electrical characteristics.
Implementation Method 1
The pre-molded chipset includes a thermally conductive substrate, at least two chips, a patterned circuit, and a first encapsulant. The at least two chips are located on the thermally conductive substrate and thermally coupled to the thermally conductive substrate.
Implementation Method 2
A chip packaging structure of the disclosure includes a heat dissipation substrate, a pre-molded chipset, an interconnection, and a second encapsulant. The pre-molded chipset is located on the heat dissipation substrate.
Implementation Method 3
The first encapsulant covers the at least two chips and part or all of the patterned circuit. The second encapsulant covers part of the heat dissipation substrate, part or all of the interconnection, and part or all of the pre-molded chipset.
Data Source
AI summary
A chip packaging structure includes a heat dissipation substrate, a pre-molded chipset, an interconnection and a second encapsulant. The pre-molded chipset is located on the heat dissipation substrate. The interconnection is located in the packaging structure and electrically connects the heat dissipation substrate and the pre-molded chipset. The second encapsulant covers part of the heat dissipation substrate, part or all of the interconnection, and part or all of the pre-molded chipset. The pre-molded chipset includes a thermally conductive substrate, at least two chips, a patterned circuit, and a first encapsulant. The patterned circuit is located in the pre-molded chipset. At least two chips are electrically connected by the patterned circuit. The first encapsulant covers at least two chips and part or all of the patterned circuit. A manufacturing method of a chip packaging structure is also provided.