Chip Package Substrate Warpage Prevention Using Carrier Support

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Solution Overview

Problem

The semiconductor industry faces challenges in manufacturing thin and large-sized substrates, which easily warp, leading to decreased yield rates due to difficulties in processing.

Innovation Solution

A method for making a stackable chip package using a substrate with conductive vias and bumps, where a carrier and encapsulation support the substrate to prevent warpage, involving steps like substrate placement on a carrier, formation of through vias, chip mounting, encapsulation, and removal of the carrier and encapsulation before completion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Weight of moving object

If substrates with large size and thin thickness are used for mass-manufacturing, then the product can be light, thin and small, but warpage of the substrates occurs easily making the manufacturing process difficult

Engineering Contradiction:
Improvesubstrate thicknessVSAvoidsubstrate warpage
Core Design Contradiction:
Weight of moving objectVSManufacturing precision

Solution Approach 1:

The patent introduces a carrier as an intermediary substrate to support the thin substrate during manufacturing processes. The carrier provides mechanical strength and stability, preventing warpage of the thin substrate while allowing standard manufacturing processes to be used. After bonding, the carrier can be removed, leaving the thin substrate intact.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Length of moving object

If substrates with large size and thin thickness are used, then the product achieves desired thinness, but the manufacturing process becomes difficult and yield rate decreases

Engineering Contradiction:
Improvesubstrate thicknessVSAvoidyield rate
Core Design Contradiction:
Length of moving objectVSProductivity

Solution Approach 1:

The carrier acts as a temporary support structure that enables standard manufacturing processes to be applied to thin substrates without causing warpage-related defects. This intermediary approach maintains high yield rates by preventing manufacturing failures while allowing the final product to achieve the desired thin dimensions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The substrate is bonded to the carrier before undergoing manufacturing processes such as thinning, patterning, and assembly. This preliminary support structure prevents warpage during these critical processes, ensuring high yield rates. The carrier is removed only after the manufacturing is complete, having served its protective function throughout.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8691625B2Method for making a chip package
Publication Date: 2014.04.08 ADVANCED SEMICON ENG INC
  • US8691625B2 patent drawing
  • US8691625B2 patent drawing
  • US8691625B2 patent drawing

AI summary

The present invention relates to a method for making a chip package. The method includes the following steps: (a) providing a substrate having at least one conductive via; (b) disposing the substrate on a carrier; (c) removing part of the substrate, so as to expose the conductive via, and form at least one through via; (d) disposing a plurality of chips on a surface of the substrate, wherein the chips are electrically connected to the through via of the substrate; (e) forming an encapsulation; (f) removing the carrier; (g) conducting a flip-chip mounting process; (h) removing the encapsulation; and (i) forming a protective material. Whereby, the carrier and the encapsulation can avoid warpage of the substrate during the manufacturing process.