Wafer-Level Chip Package With Support Layer
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Solution Overview
Problem
The miniaturization of electronic products requires improved chip package technology to handle scaled-down chips without damaging them during the packaging process.
Innovation Solution
A chip package is formed using a semiconductor substrate with a dielectric layer, conducting pad structures, a support layer, and a protection layer, where the substrate is thinned and processed to create separate chip packages using a wafer-level package process, including scribing, bonding, and cutting, to minimize damage and reduce manufacturing costs and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If chips are scaled down to meet miniaturization requirements, then electronic product size is reduced, but chip structural strength decreases making them more susceptible to damage during packaging
Solution Approach 1:
The patent applies preliminary action by forming a support layer on the chip surface before the thinning process. This support layer provides structural reinforcement during subsequent processing steps, preventing chip damage while enabling the final miniaturized thickness to be achieved. The support layer is temporarily present during critical operations and then removed after packaging is complete.
Solution Approach 2:
The patent employs parameter changes by temporarily modifying the chip's structural parameters during processing. The support layer changes the mechanical properties and thickness parameters of the chip during packaging operations, allowing thin chips to be handled with the structural integrity of thicker chips. After packaging, the support layer is removed and parameters return to the final miniaturized state.
2Ease of manufacture
If conventional packaging processes are used on scaled-down chips, then existing manufacturing capabilities are maintained, but chip damage occurs during processing
Solution Approach 1:
The support layer acts as an intermediary element between the chip and the packaging process. It mediates the interaction between conventional packaging equipment and fragile miniaturized chips, providing the necessary structural support during handling, bonding, and cutting operations without requiring modification of existing manufacturing processes.
3Productivity
If wafer-level packaging is implemented to reduce costs and time, then manufacturing efficiency is improved, but new process steps are required that increase process complexity
Solution Approach 1:
The patent applies segmentation by dividing the packaging process into distinct phases: support layer formation, wafer-level processing, and support layer removal. This segmentation allows each phase to be optimized independently while maintaining overall process efficiency. The support layer enables wafer-level processing of multiple chips simultaneously, dramatically improving productivity despite the additional process steps.
Data Source
AI summary
An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure located in the dielectric layer and electrically connected to the device region, wherein the conducting pad structure comprises a stacked structure of a plurality of conducting pad layers; a support layer disposed on a top surface of the conducting pad structure; and a protection layer disposed on the second surface of the semiconductor substrate.