Chip Package Layout With Symmetric Wiring for Uniform Bandwidth
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Solution Overview
Problem
Existing system-in-package structures face communication rate disparities and increased wiring complexity due to asymmetric wiring lengths between logic chips, affecting performance and bandwidth.
Innovation Solution
A package structure with symmetric wiring lengths in both row and column directions, utilizing a substrate with discrete first and second wirings, and a chip arrangement that ensures consistent communication rates across different directions by interconnecting adjacent chips through equal-length wirings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wiring is performed in the X direction between adjacent logic chips, then interconnection is achieved, but the wiring length increases compared to Y direction wiring, resulting in lower communication rate
Solution Approach 1:
The patent applies asymmetry by strategically placing memory chips in the X direction to act as intermediaries, transforming the asymmetric wiring length problem into a symmetric communication architecture where both X and Y direction logic chips achieve equal communication rates through equal-length wiring paths
2Adaptability or versatility
If memory chips are mounted between adjacent logic chips in the X direction, then interconnection is enabled, but wiring complexity and difficulty increase
Solution Approach 1:
The patent uses memory chips as intermediary elements positioned between logic chips in the X direction. These intermediaries enable interconnection while maintaining symmetric wiring lengths, thereby reducing wiring complexity compared to direct long-distance wiring between logic chips
3Productivity
If asymmetric wiring lengths are used in different directions, then chip interconnection is achieved, but bandwidth and performance are limited
Solution Approach 1:
The patent achieves equipotentiality in communication performance by designing symmetric wiring paths of equal length between adjacent logic chips in both X and Y directions. This ensures equal signal transmission quality and consistent communication rates, maximizing bandwidth utilization across the entire chip array
Data Source
AI summary
A package structure and a forming method thereof are disclosed. In the package structure, two adjacent first chips arranged in a row direction are interconnected through a first wiring, two adjacent first chips arranged in a column direction are interconnected through a second wiring, and lengths of the first wiring and the second wiring are the same, so that two adjacent first chips can be interconnected in both the row direction and the column direction, thereby increasing connection channels and enhancing the bandwidth. In addition, since the lengths of the first wiring and the second wiring are the same, rates for various same or different communications or data transmissions between the two adjacent first chips arranged in rows and columns can remain consistent or vary slightly in the row direction and the column direction, thereby improving performance of the package structure.