Semiconductor Chip Package Terminal Arrangement Freedom
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Solution Overview
Problem
Existing semiconductor chip packages face challenges in downsizing while maintaining the freedom of arrangement for external terminals, as they are typically limited to the periphery of the chip, restricting the number and arrangement of external terminals.
Innovation Solution
A semiconductor chip package design that includes a resin layer surrounding the chip, with through-electrodes formed in both the resin layer and the chip, allowing external terminals to be arranged in both regions, enhancing the freedom of terminal arrangement and reducing package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external terminals are arranged only in the periphery region of the semiconductor chip, then the package structure is simple, but the freedom of arrangement of external terminals is limited and the number of external terminals is restricted
Solution Approach 1:
The patent extends the arrangement space of external terminals from the two-dimensional periphery region to include the resin layer region, effectively utilizing the third dimension (depth/thickness) of the package structure. Through-electrodes are formed in the resin layer to enable terminal arrangement in this additional spatial region, thereby increasing freedom of arrangement without significantly complicating the overall package structure.
Solution Approach 2:
The package structure is segmented into two distinct regions: the periphery region of the semiconductor chip and the resin layer region. Each region can independently accommodate external terminals through different connection methods (peripheral terminals connected to chip electrodes, and resin layer terminals connected via through-electrodes), thereby expanding the total arrangement freedom while maintaining structural clarity.
2Adaptability or versatility
If external terminals are arranged in both the periphery region and resin layer region, then the freedom of arrangement and number of external terminals increase, but the manufacturing process becomes more complex
Solution Approach 1:
The resin layer is formed and through-electrodes are prepared in advance before the semiconductor chip is mounted. This preliminary preparation of the resin layer region allows for subsequent easy connection of external terminals to through-electrodes, reducing the overall manufacturing complexity despite adding functionality. The through-electrodes are pre-positioned in the resin layer, making the final assembly process straightforward.
3Volume of moving object
If the package size is reduced for downsizing, then the electronic apparatus becomes more compact, but the arrangement space for external terminals is limited
Solution Approach 1:
By utilizing the resin layer region (vertical/thickness dimension) for terminal arrangement, the patent effectively increases the available arrangement space without increasing the horizontal footprint of the package. This allows compact package sizing while maintaining adequate space for multiple external terminals through three-dimensional spatial utilization.
Solution Approach 2:
The resin layer acts as a flexible structural element that can be optimized in thickness to provide adequate space for through-electrodes and external terminals. By adjusting the resin layer thickness parameter, the package can achieve downsizing in horizontal dimensions while maintaining sufficient vertical space for terminal arrangements, thus resolving the contradiction between compact size and terminal arrangement space.
Data Source
AI summary
This semiconductor chip package has opposed first surface and second surface, and includes a semiconductor chip having a circuit part and an electrode for supplying a voltage to the circuit part, a resin layer formed in a periphery of the semiconductor chip, a substrate that is disposed to face the first surface of the semiconductor chip and the resin layer, and a plurality of external terminals that are provided on the second surface of the semiconductor chip, each of the plurality of external terminals being electrically coupled to any of the plurality of electrodes.