Chip Package Structure With Thermal Coupling for Multi-Chip Heat Dissipation
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Solution Overview
Problem
Integrated circuit packages face challenges with heat dissipation, leading to performance degradation, warping, delamination, and cracking, and the integration of chips of different sizes complicates the manufacturing process, affecting efficiency and reliability.
Innovation Solution
A chip package structure is designed with a heat dissipation base, redistribution layers, metal stacks, conductive structures, and an encapsulant, where the second redistribution layer is thermally coupled to the heat dissipation base, and the inactive surfaces of the chips are thermally coupled to the second redistribution layer via metal stacks, facilitating efficient heat dissipation and alignment of chips during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chips of different sizes are integrated into the same package, then functional integration is improved, but manufacturing process complexity increases
Solution Approach 1:
The package structure is segmented into distinct functional layers: a support substrate for mechanical stability, a first redistribution layer for electrical routing, and a second redistribution layer with thermal coupling structures for heat management. This segmentation allows each layer to be optimized independently, simplifying the manufacturing process while supporting multi-chip integration.
Solution Approach 2:
The patent introduces intermediary structures including the support substrate as a mechanical foundation, redistribution layers as electrical intermediaries, and thermal coupling structures as thermal intermediaries. These intermediaries facilitate the integration of chips with different sizes by providing standardized interfaces and coupling mechanisms, thereby reducing manufacturing complexity.
2Temperature
If heat dissipation is improved through thermal coupling structures, then thermal management is improved, but device structure complexity increases
Solution Approach 1:
The patent merges multiple functions into integrated structures: the support substrate serves both as a mechanical foundation and a thermal pathway; the redistribution layers simultaneously provide electrical routing and thermal coupling. This merging reduces the need for separate dedicated thermal management components, thereby limiting the increase in structural complexity while improving heat dissipation.
Solution Approach 2:
The support substrate and redistribution layers are designed with multi-functionality, serving both mechanical support, electrical routing, and thermal management functions. This universality allows a single structure to perform multiple roles, improving heat dissipation without proportionally increasing device complexity.
3Temperature
If thermal coupling structures are added to manage heat, then heat dissipation is improved, but manufacturing difficulty increases
Solution Approach 1:
The support substrate and redistribution layers are prepared in advance with pre-formed thermal coupling structures and electrical routing patterns. Chips are then mounted onto these pre-prepared structures, allowing thermal management features to be integrated without adding significant manufacturing difficulty during the chip assembly process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively manages heat dissipation, preventing thermal stress-related issues and improving the reliability and electrical properties of the chip package, while also enhancing the efficiency of the manufacturing process by stabilizing chip alignment and transfer.
Implementation Method 1
The second redistribution layer is disposed on the heat dissipation base and thermally coupled to the heat dissipation base
Implementation Method 2
the plurality of inactive surfaces of the plurality of chips are thermally coupled to the second redistribution layer via the plurality of metal stacks
Data Source
AI summary
A chip package structure including a heat dissipation base, a first redistribution layer, a second redistribution layer, at least one chip, at least one metal stack, a plurality of conductive structures, and an encapsulant is provided. The second redistribution layer is disposed on the heat dissipation base and thermally coupled to the heat dissipation base. The chip, the metal stack, and the conductive structures are disposed between the second redistribution layer and the first redistribution layer. An active surface of the chip is electrically connected to the first redistribution layer and an inactive surface of the chip is thermally coupled to the second redistribution layer via the metal stack. The first redistribution layer is electrically connected to the second redistribution layer via the conductive structures. The encapsulant is filled between the second redistribution layer and the first redistribution layer. A manufacturing method of a chip package structure is also provided.