Chip Package Thermal Dissipation Structure for 3DIC Heat Management

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Solution Overview

Problem

The packaging of semiconductor dies in three-dimensional integrated circuits (3DICs) faces challenges with heat dissipation, which affects the electrical performance and reliability of the devices, particularly in package-on-package (PoP) structures where heat generated from semiconductor dies can negatively impact device performance.

Innovation Solution

A thermal dissipation structure is integrated into the chip package, comprising heat-spreading layers and cap layers in an alternate arrangement, which improves thermal transfer rates without the need for additional thermal interface materials (TIM) and minimizes package height by forming these layers directly on the base layer or over hot spot regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If semiconductor dies are stacked in PoP structure to integrate various packages, then device functionality and integration are improved, but heat dissipation capability deteriorates and thermal management becomes difficult

Engineering Contradiction:
Improvepackage integrationVSAvoidheat dissipation
Core Design Contradiction:
Adaptability or versatilityVSTemperature

Solution Approach 1:

The patent divides the thermal management system into multiple heat-spreading layers positioned at different locations within the package structure. These layers segment the heat dissipation function across multiple zones, allowing heat to be dispersed and managed at different levels rather than concentrating thermal load in a single location.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces heat-spreading layers as intermediary thermal management components between the semiconductor dies and the external environment. These layers act as mediators that facilitate heat transfer and distribution, improving thermal management without interfering with the PoP stacking architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Temperature

If thermal interface materials are added to improve heat transfer, then thermal transfer rate is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improvethermal transfer rateVSAvoidmanufacturing complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent merges the heat-spreading layers directly with existing package structures such as substrates or interposers, eliminating the need for separate thermal interface materials. This integration combines thermal management functionality with structural components, reducing overall device complexity and manufacturing steps.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The heat-spreading layers are designed to serve multiple functions simultaneously: they provide thermal management while also serving as structural support or electrical interconnection elements. This multi-functionality eliminates the need for dedicated thermal interface materials and reduces overall component count.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Temperature

If heat-spreading layers are added to manage thermal dissipation, then thermal transfer rate is improved, but package height increases

Engineering Contradiction:
Improvethermal transfer rateVSAvoidpackage height
Core Design Contradiction:
TemperatureVSLength of stationary object

Solution Approach 1:

The patent transitions thermal management from a vertical approach (adding layers that increase height) to a lateral approach (integrating heat-spreading layers within existing horizontal planes of the package structure). This dimensional shift allows effective heat dissipation without increasing package height.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The heat-spreading layers are nested within the existing package structure, fitting into available spaces between semiconductor dies and package substrates. This nesting approach incorporates thermal management functionality without adding external volume or increasing overall package dimensions.

Inventive Principle:
Principle #7Nested doll (Nesting)

4Temperature

If semiconductor die thickness is increased to improve heat dissipation, then thermal management is improved, but manufacturing precision and device dimensions are affected

Engineering Contradiction:
Improveheat dissipationVSAvoiddie thickness control
Core Design Contradiction:
TemperatureVSManufacturing precision

Solution Approach 1:

The patent extracts the thermal management function from the semiconductor die itself and relocates it to separate heat-spreading layers within the package structure. This extraction allows the die to maintain its original thin profile and manufacturing specifications while still achieving effective heat dissipation through the dedicated thermal layers.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively enhances thermal transfer rates, reduces manufacturing costs, and maintains package height, thereby improving the reliability and performance of chip packages by efficiently managing heat without increasing semiconductor die thickness.

Implementation Method 1

heat-spreading layers and cap layers in an alternate arrangement, which improves thermal transfer rates

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20180019183A1Chip package with thermal dissipation structure and method for forming the same
Publication Date: 2018.01.18 PARABELLUM STRATEGIC OPPORTUNITIES FUND LLC
  • US20180019183A1 patent drawing
  • US20180019183A1 patent drawing
  • US20180019183A1 patent drawing

AI summary

Structures and formation methods of a chip package are provided. The chip package includes a first package structure including a first semiconductor die that has a first side and a second side opposite thereto. The chip package also includes a package layer partially or completely encapsulating the first semiconductor die, and a conductive feature in the package layer. The chip package further includes a first heat-spreading layer over the first side of the first semiconductor die and a first cap layer on the first heat-spreading layer.