Chip Package Layout With Vertical Heat Conduction Paths

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Solution Overview

Problem

Existing chip packaging methods face limitations in heat dissipation capability due to limited exposure and flexibility of heat conduction elements, which are often far away from the bottom plate and have restricted layout, leading to inefficient heat dissipation.

Innovation Solution

The method involves forming multiple vertical heat conduction elements on a wafer or chip units, cutting them into individual units, and disposing them on a base material with through-holes, allowing the elements to directly connect or pass through, enhancing heat transfer paths to the base material.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If wirings are used for heat conduction in prior art, then electromagnetic protection is provided, but heat dissipation capability is limited due to wirings being far from the bottom plate and having small exposed areas

Engineering Contradiction:
Improveheat dissipation capabilityVSAvoiddistance from bottom plate
Core Design Contradiction:
TemperatureVSLength of moving object

Solution Approach 1:

The patent transitions from planar heat conduction (wirings on the surface) to vertical heat conduction by introducing heat conduction posts that extend downward through the package material to the bottom plate, utilizing the vertical dimension to reduce heat transfer distance and improve dissipation efficiency

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces heat conduction posts as intermediary elements between the chip unit and the bottom plate, providing a dedicated thermal pathway that mediates heat transfer and overcomes the limitation of using wirings that are both too far from the bottom plate and too small in exposed area

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If wirings are used for heat conduction, then electromagnetic protection is achieved, but layout flexibility is restricted due to wire bond rules

Engineering Contradiction:
Improvelayout flexibilityVSAvoidelectromagnetic protection
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent separates the electromagnetic protection function (performed by wirings forming a Faraday cage) from the heat conduction function (performed by dedicated heat conduction posts), allowing each to be optimized independently without the layout constraints that previously limited both functions when using wirings for both purposes

Inventive Principle:
Principle #1Segmentation

3Temperature

If vertical heat conduction elements are introduced, then heat dissipation is significantly improved, but manufacturing complexity increases

Engineering Contradiction:
Improveheat dissipation capabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent combines the formation of heat conduction posts with the existing mold packaging process, where posts are positioned in molds and the package material is molded around them, integrating the vertical heat conduction feature into the standard manufacturing flow rather than requiring separate complex assembly steps

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly improves heat dissipation capability by providing direct and efficient heat transfer paths from the chip units to the base material, utilizing high-heat-conductivity materials like copper or aluminum for the vertical elements.

Implementation Method 1

multiple vertical heat conduction elements are formed on the wafer or the chip units... the vertical heat conduction elements directly connect to the base material... significantly improves heat dissipation capability by providing direct and efficient heat transfer paths from the chip units to the base material

Methodology Applied
Scientific EffectHeat conduction: Conduction (thermal)

Data Source

PatentUS12512395B2Chip packaging method and chip package unit
Publication Date: 2025.12.30 RICHTEK TECH
  • US12512395B2 patent drawing
  • US12512395B2 patent drawing
  • US12512395B2 patent drawing

AI summary

A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.