Semiconductor Package Layout for Integration With Thermal Separation
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving higher integration levels due to the limitations of using multiple metal leads for conduction paths, which hinder efficient heat dissipation and integration.
Innovation Solution
The semiconductor device incorporates a substrate with a conductive section, a heat-dissipative lead, and a semiconductor chip, where the control chip is electrically connected to the conductive section and spaced apart from the semiconductor chip, with a resin encapsulating all components to enhance integration and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple metal leads are employed to increase conduction paths for control signals, then the number of control signals that can be handled increases, but the integration level of the semiconductor device decreases and heat dissipation becomes more difficult
Solution Approach 1:
The patent transitions from planar metal lead connections to three-dimensional wire bonding, allowing conduction paths to extend vertically above the substrate surface. This dimensional change enables multiple control signals to be transmitted through stacked wire bonds without increasing the footprint area, thereby maintaining high integration level while accommodating increased signal complexity
Solution Approach 2:
The patent introduces an intermediary conductive structure (wire bonds) that mediates between the substrate and control chip. This intermediary enables signal transmission while allowing thermal management to be handled separately through the substrate, decoupling the signal routing complexity from the integration layout constraints
2Adaptability or versatility
If multiple metal leads are employed to increase conduction paths for control signals, then the number of control signals that can be handled increases, but heat dissipation characteristics deteriorate
Solution Approach 1:
The patent segments the functional roles of different components: the substrate is dedicated to heat dissipation while wire bonds are dedicated to signal transmission. This segmentation allows the substrate to maintain its thermal management function without being compromised by additional metal leads, while still enabling increased control signal capacity through the wire bonding structure
Solution Approach 2:
The patent replaces the conventional metal lead system with a wire bonding system that separates thermal and electrical functions. The substrate continues to provide thermal conduction pathways, while the wire bonds provide electrical connectivity without significantly adding to thermal load, thus maintaining heat dissipation characteristics while increasing signal handling capacity
3Device complexity
If control chip is positioned close to semiconductor chip for electrical connection, then integration level increases, but heat dissipation pathways are blocked
Solution Approach 1:
The patent positions the control chip in a different spatial dimension relative to the semiconductor chip, connecting them through vertical wire bonds rather than horizontal proximity. This allows the control chip to be electrically connected while maintaining physical separation that preserves heat dissipation pathways, achieving high integration without thermal interference
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a higher level of integration while maintaining effective heat dissipation characteristics, enabling more efficient operation of semiconductor devices.
Implementation Method 1
a first lead located on the substrate and more heat-dissipative than the substrate
Data Source
AI summary
A semiconductor device A1 includes a substrate 3, a conductive section 5 formed on the substrate 3 and including a conductive material, a lead 1A located on the substrate 3, a semiconductor chip 4A located on the lead 1A, a control chip 4G located on the substrate 3 and electrically connected to the conductive section 5 and the semiconductor chip 4A for controlling an operation of the semiconductor chip 4A, and a resin 7 covering the semiconductor chip 4A, the control chip 4G, at least a part of the substrate 3 and a part of the lead 1A. This configuration contributes to achieving a higher level of integration of the semiconductor device.