Chip Package With Molding Compound Through Holes
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Solution Overview
Problem
Existing chip packages face challenges in size adjustment due to the limitations of silicon chips, leading to increased material and manufacturing costs, and complexity in processing multiple-function packages, which also results in leakage and parasitic capacitance issues.
Innovation Solution
A chip package design featuring a first chip, a second chip, and a molding compound with through holes, allowing for flexible size selection and electrical connection without the need for etching, using a carrier with distribution lines to facilitate electrical connections and reduce material costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of the silicon chip is adjusted to fulfill product requirements, then the size of the chip package can be changed, but the material and manufacturing cost of the silicon chip increases
Solution Approach 1:
The invention divides the chip package into multiple independent chips (first chip and second chip) with different functions. The first chip handles sensor functions while the second chip handles processing functions. This segmentation allows each chip to be optimized independently, enabling the chip package size to be adjusted by selecting appropriate chip sizes for each function without necessarily increasing the cost of individual silicon chips.
Solution Approach 2:
The invention transitions from a single-plane chip layout to a three-dimensional stacked architecture where the first chip and second chip are positioned at different vertical levels. This dimensional change allows the chip package to achieve larger functional capacity without proportionally increasing the footprint area, thereby adjusting package size efficiently without linearly increasing material costs.
2Reliability
If the chip undergoes an etching process to form a through hole that exposes a conductive pad, then the distribution line can be electrically connected to the conductive pad, but the processing complexity increases and leakage and parasitic capacitance are generated
Solution Approach 1:
The invention extracts the electrical connection function from the substrate plane by forming vertical through-holes that penetrate the substrate. This allows conductive pads to be exposed on the front surface without requiring complex planar routing, simplifying the distribution line connection process and reducing processing complexity while maintaining reliable electrical connection.
Solution Approach 2:
The invention introduces filling material into the through-holes to create conductive pathways. This intermediary material serves as a mediator between the conductive pads and the distribution lines, enabling electrical connection without direct exposure of conductive pads on the substrate surface, thereby reducing leakage and parasitic capacitance while maintaining connection reliability.
3Reliability
If the chip undergoes an etching process to form a through hole that exposes a conductive pad, then the distribution line can be electrically connected to the conductive pad, but leakage and parasitic capacitance are generated
Solution Approach 1:
The invention introduces filling material into the through-holes to create conductive pathways. This intermediary material serves as a mediator between the conductive pads and the distribution lines, enabling electrical connection without direct exposure of conductive pads on the substrate surface, thereby reducing leakage and parasitic capacitance while maintaining connection reliability.
Solution Approach 2:
The invention uses a protective layer (thin film) to cover the front surface of the substrate, including the through-holes. This thin film structure provides insulation and protection, preventing leakage currents and reducing parasitic capacitance associated with exposed conductive pads, while still allowing electrical connection through the filled through-holes.
Data Source
AI summary
A chip package includes a first chip, a second chip, a first molding compound, and a first distribution line. The second chip vertically or laterally overlaps the first chip. The second chip has a conductive pad. The first molding compound covers the first and second chips, and surrounds the second chip. The first molding compound has a first through hole. The conductive pad is in the first through hole. The first distribution line is located on a surface of the first molding compound facing away from the second chip, and electrically connects the conductive pad in the first through hole.