Chip Package Stiffener Cavity for TIM Leakage Containment

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Solution Overview

Problem

Conventional chip package assemblies suffer from thermal interface material (TIM) leakage, which can short surface mounted components and overflow onto the printed circuit board, leading to production defects and reduced functionality.

Innovation Solution

A chip package assembly design incorporating a stiffener with an internal cavity that redirects excess TIM into a containment space within the stiffener, preventing leakage and overflow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a foam or gasket is applied around the outside of the package to prevent TIM leakage, then TIM containment is improved, but the space available for dies is reduced and the package substrate size increases

Engineering Contradiction:

ImproveTIM containmentVSAvoidpackage substrate area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The cavity is nested within the stiffener structure itself, utilizing the existing stiffener volume to contain TIM. This eliminates the need for external foam or gasket additions, as the containment feature is integrated into the existing package architecture rather than adding external containment layers

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The solution transitions from two-dimensional containment (foam/gasket around the perimeter) to three-dimensional containment by creating a vertical cavity within the stiffener. The TIM is contained within this subsurface volume, utilizing the vertical dimension rather than requiring lateral expansion of the package substrate

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If the space for surface mounted components is sufficiently spaced from both the dies and the stiffener to prevent TIM leakage, then TIM containment is improved, but the component density and functionality are reduced

Engineering Contradiction:

ImproveTIM containmentVSAvoidcomponent density

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The cavity provides localized TIM containment precisely where needed - in the region between the die and stiffener. This allows surface mounted components to be positioned closer to the die and stiffener without risk of TIM exposure, as the containment is localized to the specific hazard zone rather than requiring universal spacing

Inventive Principle:

Principle #3Local quality

3Reliability

If an insufficient amount of TIM is applied to the package to prevent leakage, then TIM containment is improved, but the thermal conduction performance is degraded

Engineering Contradiction:

ImproveTIM containmentVSAvoidthermal conduction

Core Design Contradiction:

ReliabilityVSTemperature

Solution Approach 1:

The cavity, which could be seen as wasted space, is converted into a beneficial feature that actively manages TIM overflow. This allows sufficient TIM to be applied for optimal thermal conduction without fear of leakage, as the cavity captures and contains any excess TIM that would otherwise cause defects

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The cavity acts as a pre-prepared containment buffer that is ready to receive and hold any TIM that overflows from the die-heat sink interface. This beforehand preparation eliminates the need to under-apply TIM as a preventive measure, allowing full thermal conduction performance while maintaining containment reliability

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS20250279328A1Chip package assembly with on-package containment system

Publication Date: 2025.09.04 ADVANCED MICRO DEVICES INC

AI summary

A chip package, an electronic device, and methods for fabricating the same are disclosed herein. In one example, a chip package includes a package substrate, an integrated circuit (IC) die, and a stiffener. The IC die has a first height and is mounted on a top surface of the package substrate. The stiffener is mounted to the top surface of the package substrate. A cavity is disposed in the stiffener. The cavity has an opening formed through the stiffener that faces towards the IC die.