Chip Package Structure With Uniform Micro Bumps for High Yield
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Solution Overview
Problem
The yield of chip assembly in conventional package structures is low due to size differences between micro bumps on chips and bridging elements, leading to inefficient connections.
Innovation Solution
A chip package structure with uniformly sized first micro bumps and a bridging element that includes dielectric layers and patterned circuit layers, allowing for high-density electrical connections between adjacent chips through a substrate, pads, and micro bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional EMIB technology uses different sized micro bumps for connecting chips to bridging elements and circuit carriers, then connection functionality is achieved, but assembly yield is low
Solution Approach 1:
The patent applies homogeneity by making all first micro bumps on the chips have the same size. This uniform micro bump design simplifies the assembly process and improves yield by eliminating the complexity of matching different sized micro bumps to different targets (bridging elements and circuit carrier), while maintaining all necessary connection functionalities through the standardized interface.
2Reliability
If uniformly sized first micro bumps are used for all chip connections, then assembly yield improves, but connection density capability may be limited
Solution Approach 1:
The patent resolves the density limitation by transitioning from a two-dimensional planar connection approach to a three-dimensional stacked architecture. Multiple chips are vertically stacked and interconnected through uniformly sized micro bumps, enabling high connection density through the third dimension (vertical stacking) while maintaining manufacturing simplicity through uniform micro bump dimensions.
3Adaptability or versatility
If multiple chip connections require different micro bump sizes, then specific connection requirements are met, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies universality by designing a standardized micro bump interface that serves multiple functions: connecting chips to bridging elements, connecting chips to the circuit carrier, and enabling vertical stacking. This universal interface with uniform micro bump dimensions eliminates the need for different sized micro bumps while maintaining all required connection configurations through the standardized design.
Data Source
AI summary
A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.