Chip Package Vertical Connections for Stacking Density
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Solution Overview
Problem
Conventional three-dimensional integrated circuits face challenges due to large TSVs and keep-out zones, which consume significant die area and limit the number of dies that can be stacked, causing carrier mobility variations and inefficient use of space.
Innovation Solution
The design includes a chip package with two-dimensionally arranged first, second, and vertical connections, along with conductors and insulation layers, allowing for compact arrangement of vertical connections and reduced area usage, enabling more efficient stacking of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If TSVs are arranged in a linear direction to provide vertical connections, then the three-dimensional integrated circuit can be formed, but the large size of TSVs and their keep-out zones consume significant die area, resulting in a large die or limiting the number of dies to be stacked
Solution Approach 1:
The patent transitions from conventional linear arrangement of TSVs to a two-dimensional grid arrangement. Multiple TSVs are organized in rows and columns across the die surface, allowing vertical connections to be distributed throughout the die area rather than confined to a single direction. This dimensional change maximizes space utilization and enables higher stacking density without proportionally increasing die area.
Solution Approach 2:
The patent divides the die into multiple regions with TSVs segmented into different groups (first TSVs, second TSVs, third TSVs, fourth TSVs) arranged in a grid pattern. Each segment serves specific functional purposes, allowing independent optimization of different areas and reducing the impact of keep-out zones on overall die area utilization.
2Reliability
If large TSVs are used to ensure reliable vertical connections between dies, then connection reliability is improved, but the keep-out zones surrounding TSVs create tensile stresses that cause significant carrier mobility variation
Solution Approach 1:
The patent implements different via structures in different regions of the die. First and second TSVs have one configuration, while third and fourth TSVs have another configuration, allowing local optimization of stress distribution and carrier mobility in different areas while maintaining overall connection reliability across the three-dimensional integrated circuit.
3Reliability
If keep-out zones are introduced around TSVs to prevent device influence from TSV-induced stresses, then device performance is protected, but the effective area for placing devices and cells is reduced
Solution Approach 1:
By arranging TSVs in a two-dimensional grid rather than linear fashion, the patent distributes keep-out zones across the die surface in a pattern that minimizes their cumulative impact on effective device area. The grid arrangement allows devices to be placed in the spaces between TSV columns, utilizing the available area more efficiently while still protecting device performance through adequate spacing.
Data Source
AI summary
A semiconductor device includes a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer. The semiconductor device further includes a plurality of lower vertical connections formed through the substrate and correspondingly connecting to the chip select pads and a chip select terminal. The chip select terminal electrically connects to the die circuit of the semiconductor device while the chip select pads are electrically isolated from the die circuit. The lower vertical connections and the straight vertical connection can be arranged in two dimensions.