Chip Package Layout With Vertical Heat Conduction Elements
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Solution Overview
Problem
Existing chip packaging methods have limited heat dissipation capabilities due to the distance and small exposed areas of heat conduction elements from the chip unit to the base material, restricting flexibility in layout and efficiency.
Innovation Solution
The method involves forming multiple vertical heat conduction elements on a wafer or chip units, which are then cut and disposed on a base material with through-holes, allowing the elements to pass through or directly connect to the base material, enhancing heat transfer by increasing the surface area for heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If wirings are used for heat conduction in prior art, then electromagnetic protection is provided, but heat dissipation capability is limited due to large distance and small exposed areas
Solution Approach 1:
The patent transitions from planar heat conduction (wirings on the surface) to vertical heat conduction by forming heat conduction columns that extend downward through the package material to the base material. This dimensional change from horizontal to vertical orientation dramatically reduces the heat transfer path length and increases the exposed surface area at the base material interface, thereby significantly improving heat dissipation capability.
Solution Approach 2:
The patent divides the heat conduction function into multiple discrete heat conduction columns distributed across the chip unit. Instead of relying on a few wirings, numerous columns are formed in parallel, each providing an independent heat transfer path. This segmentation increases the total heat dissipation surface area and distributes the thermal load, enhancing overall heat dissipation efficiency.
2Adaptability or versatility
If wirings are used for heat conduction, then electromagnetic protection is achieved, but layout flexibility is restricted due to wire bond rules
Solution Approach 1:
The patent replaces the mechanical wire bonding process with a direct formation process for heat conduction columns. Instead of manually or mechanically bonding wires to the chip, the columns are formed through processes such as printing conductive paste, sintering, or direct growth, eliminating the constraints of wire bond rules and providing greater layout flexibility for thermal management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves heat dissipation by providing multiple heat transfer paths with high heat transfer coefficients, effectively addressing the limitations of prior art by increasing the proximity and efficiency of heat transfer from the chip units to the base material.
Implementation Method 1
multiple vertical heat conduction elements are formed on the wafer or the chip units... the vertical heat conduction elements directly connect to the base material... significantly improves heat dissipation by providing multiple heat transfer paths with high heat transfer coefficients
Data Source
AI summary
A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.