Chip Package With Vertical Conducting Pads
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Solution Overview
Problem
Current chip packages face challenges in achieving high-density conducting routes and improving structural reliability as chip sizes shrink, particularly in forming effective through-substrate vias that maintain electrical connectivity and structural integrity.
Innovation Solution
A chip package design involving a substrate with conducting pads, a dielectric layer, and a conducting layer formed within a trench and hole structure, where the conducting layer electrically connects to the pads, enhancing the structural reliability and density of conducting routes through a wafer-scale package process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If chip size is reduced to achieve miniaturization, then device size decreases, but conducting route density and structural reliability deteriorate
Solution Approach 1:
The patent transitions from planar conducting routes to three-dimensional vertical conducting structures through TSVs and multi-level pad arrangements. Conducting pads are positioned at different depths (first, second, and third conducting pads at progressively lower levels), creating vertical electrical pathways that increase route density without expanding chip footprint, thereby maintaining reliability during miniaturization
Solution Approach 2:
The patent implements nested conducting structures where multiple conducting pads are arranged in vertical stacks within the substrate thickness. The first conducting pad is positioned highest, followed by the second conducting pad at a lower level, and the third conducting pad at the lowest level, creating a nested configuration that maximizes conducting route density within the limited chip volume while preserving structural integrity
2Volume of moving object
If chip size is reduced to achieve miniaturization, then device size decreases, but conducting route density deteriorates
Solution Approach 1:
The patent utilizes the vertical dimension by positioning conducting pads at different depths within the substrate. Multiple TSVs extend vertically through the substrate thickness, and conducting pads are arranged in vertical stacks (first pad highest, second pad intermediate, third pad lowest), transforming two-dimensional conducting routes into three-dimensional pathways that significantly increase route density within the miniaturized chip volume
Solution Approach 2:
The patent segments the conducting pathway into multiple discrete vertical elements (individual TSVs) that are distributed throughout the substrate. Each TSV provides an independent conducting route, and multiple TSVs can be packed closely together, allowing the conducting route density to be increased by simply adding more segmented vertical pathways within the limited chip area
Data Source
AI summary
A method for forming a chip package, by providing a substrate having a plurality of conducting pads below a lower surface, and a dielectric layer located between the conducting pads, forming a recess in an upper surface of the substrate, forming a hole extending through the bottom of the recess, forming an insulating layer on the sidewall of the recess and in the hole, exposing a portion of the conducting pads through the insulating layer, and forming a conducting layer on the insulating layer and through the hole to contact with the conducting pads.