Integrated Chip Package Structure Without Through-Substrate Vias
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Solution Overview
Problem
New packaging technologies for semiconductor dies face manufacturing challenges in achieving higher density and functionality while maintaining performance and reliability, particularly in the absence of through substrate vias which limits routing space and increases complexity.
Innovation Solution
The formation of package structures using a substrate with dies or packages and a protective element that also functions as a warpage-control and heat dissipation element, along with the use of via tower structures as backside power rails, eliminates the need for through substrate vias, allowing for direct bonding of chip structures and enhancing bonding surfaces through planarization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If through substrate vias are used for routing, then electrical connections can be established, but routing space is limited and device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional routing on the substrate surface to three-dimensional routing using via tower structures that extend vertically through the substrate. This dimensional change provides additional routing pathways and increases available routing space without confining connections to the substrate plane, thereby resolving the routing space limitation while managing complexity through structured vertical interconnections.
Solution Approach 2:
The patent divides the substrate into multiple segments or layers with via towers penetrating through specific regions. This segmentation allows routing to be distributed across different vertical levels and substrate regions, increasing routing capacity and reducing the complexity of any single routing layer by breaking down the monolithic substrate into functional zones.
2Adaptability or versatility
If keep-out zones are maintained around through substrate vias, then via placement is constrained, but routing flexibility is reduced
Solution Approach 1:
The patent implements nested via tower structures where multiple vias are arranged in concentric or layered patterns within a unified via tower footprint. This nesting approach allows multiple routing paths to be accommodated within a single keep-out zone, effectively reducing the lateral space required per via while maintaining routing flexibility through the nested arrangement of conductive pathways.
3Productivity
If chip structures are bonded directly without through substrate vias, then bonding efficiency improves, but interconnection routing becomes more challenging
Solution Approach 1:
The patent performs preliminary routing and interconnection establishment through via tower structures before the final chip bonding process. By pre-configuring the vertical interconnection pathways and testing the interconnect integrity prior to bonding, the system enables direct chip-to-chip bonding without requiring through-substrate via formation after bonding, thereby improving bonding efficiency while managing routing complexity through advance preparation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance and reliability of the package structure by eliminating the need for keep-out zones, increasing routing space, and enhancing bonding efficiency, leading to more efficient and reliable three-dimensional packaging solutions.
Implementation Method 1
bonding a second chip structure to the first chip structure using dielectric-to-dielectric bonding and metal-to-metal bonding
Implementation Method 2
bonding a second chip structure to the first chip structure using dielectric-to-dielectric bonding and metal-to-metal bonding
Implementation Method 3
enhancing bonding surfaces through planarization processes
Implementation Method 4
a protective element that also functions as a warpage-control and heat dissipation element
Data Source
AI summary
A package structure and a formation method are provided. The method includes disposing a first chip structure over a carrier substrate. The first chip structure has a front-side interconnection structure facing the carrier substrate. The method also includes forming a back-side interconnection structure over the first chip structure. The first chip structure has a device portion between the back-side interconnection structure and the front-side interconnection structure. The back-side interconnection structure has stacked conductive vias. The method further includes bonding a second chip structure to the first chip structure using dielectric-to-dielectric bonding and metal-to-metal bonding.