Chip Package With Through-Substrate Vias for Size Reduction
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Solution Overview
Problem
Multi-chip package structures face challenges in reducing size and increasing fabrication costs due to the need for extensive bonding wires, which is not suitable for portable electronic products.
Innovation Solution
A chip package design involving a first substrate, a second substrate with penetrating openings defining conducting regions, a carrier substrate, an insulating layer filling these openings, and a conducting layer electrically contacting the conducting regions, allowing for efficient electrical connection without the need for extensive bonding wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires are used to electrically connect multiple chips, then electrical connectivity is achieved, but the package size increases and fabrication cost increases
Solution Approach 1:
The patent transitions from planar bonding wire connections to three-dimensional vertical interconnections through through-substrate vias. Multiple conducting regions are stacked vertically within the substrate, allowing electrical connections between chips in the vertical dimension rather than requiring extensive lateral bonding wire routing, thereby reducing package footprint while maintaining connectivity
Solution Approach 2:
The patent implements nested conducting regions where multiple conducting regions are positioned at different depths within the substrate, with upper conducting regions nested above lower conducting regions. This vertical nesting allows multiple electrical connections to be packed within the substrate volume without increasing lateral package dimensions
2Reliability
If bonding wires are used to electrically connect multiple chips, then electrical connectivity is achieved, but fabrication cost increases
Solution Approach 1:
The patent merges the electrical connection function with the substrate structure itself by forming conducting regions directly within the substrate material through doping or conductor deposition. This integrates multiple functions (substrate support and electrical interconnection) into a single component, eliminating the need for separate bonding wire materials and processes, thereby reducing fabrication cost
Solution Approach 2:
The conducting regions are formed within the substrate during substrate fabrication before chip assembly. This preliminary formation of conductive pathways eliminates the need for subsequent bonding wire attachment processes, reducing manufacturing steps and associated costs while ensuring reliable electrical connections are already in place
3Adaptability or versatility
If multiple chips are integrated in a single package substrate, then multi-functionality is achieved, but the number of bonding wires increases leading to larger package size
Solution Approach 1:
The patent enables multi-chip integration by stacking conducting regions vertically within the substrate, allowing multiple functional chips to be connected in three dimensions. This vertical arrangement supports multi-functionality while maintaining a compact lateral package footprint, as connections occur through the substrate thickness rather than requiring expanded lateral bonding wire routing
Data Source
AI summary
An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate has at least one opening penetrating through the second substrate, and the at least one opening defines a plurality of conducting regions electrically insulated from each other in the second substrate; a carrier substrate disposed on the second substrate; an insulating layer disposed on a surface and a sidewall of the carrier substrate, wherein the insulating layer fills the at least one opening of the second substrate; and a conducting layer disposed on the insulating layer on the carrier substrate and electrically contacting with one of the conducting regions.