Chip Package Void Buffering CTE Mismatch Delamination
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Solution Overview
Problem
The mismatch in the coefficient of thermal expansion (CTE) between the passivation layer and the metal redistribution layer (RDL) in chip packages leads to delamination of the RDL from conductive pads, reducing the reliability of semiconductor chip packages.
Innovation Solution
A chip package structure with a void between the passivation layer and the conductive pad is created by forming a first opening with varying calibers, where an insulating layer and a redistribution layer are used, and a passivation layer covers the RDL, partially filling the opening to form a void that acts as a buffer, reducing stress and preventing delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a passivation layer is formed over a metal redistribution layer (RDL) in a chip package, then the RDL is protected and electrically connected to conductive pads, but the mismatch in coefficient of thermal expansion (CTE) between the passivation layer and metal RDL causes the RDL to peel off from the conductive pads, reducing reliability
Solution Approach 1:
A void is intentionally formed between the passivation layer and the conductive pad in advance, serving as a buffer space that absorbs thermal expansion stress before it can cause delamination. This preemptive cushioning prevents the RDL from peeling off during thermal cycling, thereby maintaining bonding reliability while accommodating CTE mismatch.
Solution Approach 2:
The void acts as an intermediary element between the passivation layer and the conductive pad, mediating the stress transfer during thermal expansion. By introducing this intermediate space, the direct stress concentration at the RDL-pad interface is reduced, preventing delamination without compromising the protective function of the passivation layer.
2Reliability
If the first opening has a varying caliber (larger at the first surface, smaller at the second surface), then the void formation is facilitated and stress distribution is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The first opening is designed with an asymmetric caliber profile, being larger at the first surface and smaller at the second surface. This asymmetric geometry optimizes stress distribution by providing more void space where thermal expansion stress accumulates, while the narrower lower portion maintains better structural integrity. The asymmetric design naturally guides stress away from the critical RDL-pad interface.
Solution Approach 2:
Different regions of the opening are given different calibers to serve different functions: the upper portion (larger caliber) provides stress relief space, while the lower portion (smaller caliber) maintains structural support and precise alignment. This local differentiation of geometric properties optimizes both stress distribution and manufacturing feasibility.
Data Source
AI summary
A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.