Chip Package with T-Contact Redistribution Layer
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Solution Overview
Problem
Chip packaging technologies face challenges in maintaining the reliability and longevity of electronic products with touch-screen functions due to contamination and physical damage from vapor or oil, which affects the sensing devices and electrical connections.
Innovation Solution
A chip package design featuring a substrate with a sensing device and conducting pads, an encapsulation layer, and a redistribution layer, where the redistribution layer forms a T-contact with the conducting pads, and a protection layer with high hardness to prevent contamination and damage, along with a wafer-level packaging process for efficient production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sensing device and conducting pad are exposed on the substrate surface, then electrical connection and sensing function are achieved, but the sensing device is contaminated and physically damaged by vapor or oil
Solution Approach 1:
The patent introduces an encapsulation layer as an intermediary between the sensing device/conducting pad and the external environment. This encapsulation layer seals the sensing device and conducting pad, preventing vapor or oil from directly contacting and contaminating these components, thereby resolving the contradiction between maintaining electrical connection functionality and protecting against environmental contamination.
2Ease of operation
If the sensing device is exposed for touch-screen function, then user interaction is enabled, but the sensing device suffers physical damage from contamination
Solution Approach 1:
The encapsulation layer serves as a protective intermediary that allows the sensing device to maintain its touch-screen functionality while being physically protected. The layer seals the sensing device against contaminants like vapor or oil that could cause physical damage, enabling the device to withstand environmental exposure during user interaction.
3Ease of manufacture
If conventional packaging methods are used, then chip packaging is achieved, but processing costs and size are reduced through wafer-level packaging
Solution Approach 1:
The patent merges the packaging process with the chip fabrication process by implementing wafer-level packaging. This approach combines multiple discrete packaging steps into a single integrated process that occurs at the wafer stage before dicing, thereby reducing processing costs and simplifying the overall manufacturing workflow while maintaining protective encapsulation of the sensing devices.
4Reliability
If discrete packaging is used, then individual chip protection is achieved, but mass production efficiency is improved through wafer-level packaging
Solution Approach 1:
The patent combines individual chip protection with mass production efficiency by performing encapsulation at the wafer level. This allows all chips on a wafer to be protected simultaneously in a single process step, maintaining the reliability benefits of individual chip protection while achieving the productivity gains of mass production through parallel processing of multiple chips.
Data Source
AI summary
A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a sensing device and a conducting pad therein. The sensing device and the conducting pad are adjacent to the first surface. The conducting pad has a sidewall laterally protruding from a sidewall of the substrate. An encapsulation layer is attached to the first surface of the substrate to cover the sensing device and the conducting pad. A redistribution layer is disposed on the second surface of the substrate and extends to contact the sidewall of the conducting pad. An end of the redistribution layer protrudes from the first surface of the substrate and is level with a third surface of the encapsulation layer that is opposite to the first surface. A method of forming the chip package is also provided.