Chip Package Protective Layer With Printed Warpage Control

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Solution Overview

Problem

New packaging technologies for semiconductor dies face manufacturing challenges in achieving high density and functionality while maintaining cost-effectiveness and reducing processing time and potential damage during the fabrication of chip packages.

Innovation Solution

A method for forming a chip package involves creating a protective layer around semiconductor dies and using a warpage-control element printed over the protective layer to prevent or compensate for warpage, thereby reducing fabrication costs and processing time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If new packaging technologies are used to improve density and functionality, then manufacturing complexity and difficulty increase

Engineering Contradiction:
Improvedensity and functionalityVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The packaging structure is divided into distinct functional layers including a base layer, protective layer, and warpage-control element layer. This segmentation allows each layer to be optimized independently for its specific function while simplifying the overall manufacturing process by enabling modular fabrication and assembly steps.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The warpage-control element is formed and positioned on the protective layer before final packaging completion. This preliminary action prevents warpage issues from developing during subsequent manufacturing steps, avoiding the need for complex corrective measures later in the process.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If traditional warpage control methods are used, then manufacturing reliability improves, but processing time and cost increase

Engineering Contradiction:
Improvemanufacturing reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The warpage-control element is integrated directly into the packaging structure by forming it on the protective layer during the same manufacturing process. This merging eliminates the need for separate warpage control steps, reducing processing time while maintaining manufacturing reliability through the inherent structural design.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The packaging structure itself provides warpage control through the integrated warpage-control element, eliminating the need for external warpage tape or separate control mechanisms. The structure serves its own warpage prevention needs, simplifying the process and reducing costs.

Inventive Principle:
Principle #25Self-service

3Reliability

If multiple separate steps are used for warpage control, then warpage prevention effectiveness improves, but manufacturing cost increases

Engineering Contradiction:
Improvewarpage prevention effectivenessVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

Multiple functions (protection, warpage control, and structural support) are combined into a single integrated packaging structure. The warpage-control element is formed as part of the protective layer fabrication process, eliminating the need for separate warpage control components and reducing overall manufacturing cost while maintaining effectiveness.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The protective layer serves multiple functions: it protects the semiconductor die, provides a substrate for the warpage-control element, and contributes to the overall structural integrity. This multi-functionality reduces the need for additional separate components, lowering manufacturing cost while maintaining warpage prevention effectiveness.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12230597B2Package structure with warpage-control element
Publication Date: 2025.02.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12230597B2 patent drawing
  • US12230597B2 patent drawing
  • US12230597B2 patent drawing

AI summary

A package structure is provided. The package structure includes a semiconductor chip and a protective layer laterally surrounding the semiconductor chip. The package structure also includes a polymer-containing element over the protective layer. The protective layer is wider than the polymer-containing element.