Chip Package Wiring Overlay for Reliable Fan-Out Fabrication

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Solution Overview

Problem

The semiconductor industry faces challenges in simplifying the fabrication process and reducing costs for integrated fan-out packages, which are crucial for heterogeneous integration between chips and systems, while maintaining improved routability and reliability.

Innovation Solution

A method for fabricating integrated fan-out packages involves forming conductive pillars on a wafer, encapsulating them with a protection layer, and creating a redistribution circuit structure with multiple inter-dielectric and redistribution conductive layers, followed by mounting conductive balls and passive components, and stacking additional packages for a package-on-package structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional fabrication processes are used for integrated fan-out packages, then manufacturing precision and reliability can be maintained, but the fabrication process becomes complex and costs increase

Engineering Contradiction:
Improvepackage reliabilityVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The fabrication process is divided into distinct stages: forming conductive pillars on wafer, encapsulating with protection layer, creating redistribution circuit structure, and mounting components. This segmentation allows each stage to be optimized independently, simplifying the overall complex fabrication process while maintaining reliability through controlled sequential processing

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Conductive pillars are formed and encapsulated with protection layers before the redistribution circuit structure is created. This preliminary action protects the pillars during subsequent processing steps, ensuring reliability is maintained while the complex redistribution circuitry can be fabricated without risking damage to underlying structures

Inventive Principle:
Principle #10Preliminary action

2Reliability

If traditional fabrication processes are used for integrated fan-out packages, then manufacturing precision and reliability can be maintained, but fabrication costs increase

Engineering Contradiction:
Improvepackage reliabilityVSAvoidfabrication cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The process is segmented into modular stages that can be performed in a sequence, allowing for better resource utilization and reduced rework. By protecting conductive pillars early and maintaining them through subsequent steps, costly repairs or re fabrication are avoided, reducing overall manufacturing costs while preserving reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The protection layer is applied to conductive pillars before creating the redistribution circuit structure. This preliminary protective measure prevents damage during complex subsequent processing, avoiding costly rework and ensuring reliability is maintained throughout manufacturing

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If conductive pillars are exposed during processing, then routing flexibility is improved, but reliability decreases due to potential damage

Engineering Contradiction:
Improverouting flexibilityVSAvoidpillar reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The protection layer is applied to conductive pillars before the redistribution circuit structure is fabricated. This preliminary protection allows the pillars to remain covered and protected throughout the routing and circuit formation processes, maintaining reliability while still achieving the desired routing flexibility through the circuit design

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The protection layer acts as an intermediary between the conductive pillars and the external environment during processing. It shields the pillars from potential damage while allowing the redistribution circuit structure to be formed around them, thus maintaining both reliability and routing flexibility

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250293028A1Method for fabricating a chip package
Publication Date: 2025.09.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250293028A1 patent drawing
  • US20250293028A1 patent drawing
  • US20250293028A1 patent drawing

AI summary

A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.