Chip Packaging Antenna Pattern Coplanar Sealing Layer
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Solution Overview
Problem
Conventional chip packaging methods require costly etching and electroplating processes for antenna pattern formation, which increases costs and hinders the thinning of electronic devices due to the antenna pattern protruding from the sealing layer.
Innovation Solution
A chip packaging structure that includes a circuit redistribution structure, a chip, and an antenna pattern with a sealing layer having an opening and a groove, where the antenna pattern is formed without the need for etching or electroplating, with a first portion covering the sidewalls of the opening and a second portion filled in the groove, ensuring the antenna pattern is coplanar with the sealing layer surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If etching and electroplating processes are used to form the antenna pattern, then the antenna pattern can be formed on the sealing layer, but the manufacturing cost increases
Solution Approach 1:
The patent extracts the antenna pattern formation process from the conventional etching and electroplating sequence. Instead of forming the antenna pattern on the sealing layer surface, the invention forms the antenna pattern within the sealing layer itself by extracting material to create a recessed antenna pattern, eliminating the need for subsequent electroplating processes.
Solution Approach 2:
The patent replaces the electroplating process (electrochemical system) with a direct etching or additive manufacturing system. The antenna pattern is formed by removing material through etching or by selectively not depositing material, substituting the complex electroplating mechanism with simpler material removal or selective deposition processes.
2Reliability
If the antenna pattern is formed on the sealing layer surface, then signal strength is enhanced, but the electronic device thickness increases
Solution Approach 1:
The patent transitions the antenna pattern from a two-dimensional surface feature to a three-dimensional recessed structure within the sealing layer. By forming the antenna pattern in the depth dimension of the sealing layer rather than on its surface, the invention maintains signal strength while avoiding additional protrusion that would increase device thickness.
Solution Approach 2:
The antenna pattern is nested within the sealing layer structure itself. The recessed antenna pattern is formed as an integral part of the sealing layer, with the antenna pattern occupying the internal volume of the sealing layer rather than adding external protrusion, similar to how a nested doll places one object inside another.
Data Source
AI summary
A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.