Dual-Interconnect Chip Packaging for Both-Side Substrate Connection
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high-speed and small-volume interconnection between chips, with limited integration level and complexity in packaging structures, particularly in realizing electrical connection between both sides of a chip.
Innovation Solution
A packaging structure and method that includes a device chip with opposing sides, a first interconnect chip bonded to the substrate, and a second interconnect chip electrically connected to both the device chip and the first interconnect chip, allowing both sides of the device chip to be electrically connected to the substrate, enhancing integration and flexibility while reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional chip manufacturing technologies are used for monolithic chip sizes, then manufacturing processes are simplified, but the ability to achieve high-speed and small-volume interconnection between chips is limited
Solution Approach 1:
The device chip is divided into two opposite sides (first side and second side), each capable of electrical connection to the substrate through separate interconnect chips. This segmentation allows independent optimization of interconnection paths from both sides, enabling high-speed interconnection while distributing the complexity across multiple simpler connection interfaces rather than requiring a complex single-sided monolithic structure.
2Adaptability or versatility
If smaller integrated circuits with Si bridge chips are used to realize interconnection, then heterogeneous chip packaging is achieved, but the packaging structure becomes complex and integration level needs improvement
Solution Approach 1:
The first interconnect chip and second interconnect chip serve multiple functions: they provide electrical connection between the substrate and both sides of the device chip, enables heterogeneous integration, and facilitate heat dissipation. This multi-functionality reduces the need for additional specialized components, simplifying the overall packaging structure while achieving heterogeneous chip integration.
Solution Approach 2:
The first interconnect chip and second interconnect chip are positioned on opposite sides of the device chip, with both interconnect chips electrically connected to the substrate. This nested arrangement allows the device chip to be embedded between two interconnect layers, creating a compact three-dimensional heterogeneous integration structure that improves integration level while managing complexity through systematic layering.
3Adaptability or versatility
If only one side of the device chip is electrically connected to the substrate, then packaging structure is simple, but the integration level and flexibility are limited
Solution Approach 1:
The electrical connection is segmented into two independent paths: one from the first side of the device chip through the first interconnect chip to the substrate, and another from the second side through the second interconnect chip to the substrate. This segmentation provides packaging flexibility by allowing independent configuration and optimization of each connection path, while the modular nature of the segments prevents excessive overall complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the integration level of packaging, enables electrical connection of both chip sides to the outside, and enhances flexibility and cost-effectiveness by using isolated interconnect chips for improved heat dissipation and signal communication.
Implementation Method 1
the first interconnect chip being electrically connected to the substrate... the second interconnect chip being electrically connected to the first interconnect chip and the device chip
Implementation Method 2
bonding the first interconnect chip to the carrier plate... bonding the first side of the device chip to the carrier plate... bonding the first side of the device chip and the side of the first interconnect chip facing away from the second interconnect chip to the bonding surface of the substrate
Data Source
AI summary
A packaging structure and a packaging method are provided The packaging method includes: bonding a first interconnect chip to a carrier plate in a first area; bonding a first side of a device chip to the carrier plate in a second area, a first chip area of the device chip being adjacent to the first interconnect chip; bonding a second interconnect chip to the first interconnect chip and the first chip area, the second interconnect chip being electrically connected to the first interconnect chip and the device chip, and the second interconnect chip exposing a second chip area; removing the carrier plate; and bonding the first side of the device chip and a side of the first interconnect chip to a bonding surface of a substrate, the first side of the device chip and the first interconnect chip being electrically connected to the substrate.