Chip-Embedded Packaging Buffer Layers for CTE Delamination
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Solution Overview
Problem
Conventional chip-embedded packaging structures face delamination issues due to thermal stresses caused by the large difference in Coefficient of Thermal Expansion (CTE) between semiconductor chips and adhesives, leading to poor bonding forces, especially in high-power chips with high heat dissipation requirements.
Innovation Solution
A component-embedded packaging structure is developed, featuring a carrier with patterned circuit layers and an insulating material, where the semiconductor chip's inactive surface is metallized with a stack of titanium, nickel, and silver layers to serve as a buffer between the chip and adhesive, preventing delamination by dispersing thermal stresses and enhancing bonding force.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a metallized film with two or three metal layers is formed on the inactive surface of the semiconductor chip, then the bonding force is improved and heat conduction is enhanced, but delamination may still occur during packaging of high power chips with high heat dissipation requirements
Solution Approach 1:
The patent applies a five-layer composite metallized film structure (Ti/Ni/Ti/Ag/Sn) on the inactive surface of the semiconductor chip. Each layer serves a specific function: Ti provides adhesion to the substrate, Ni offers oxidation resistance and intermediate bonding, the second Ti layer enhances overall adhesion, Ag provides excellent thermal and electrical conductivity, and Sn offers superior solderability. This composite structure resolves the contradiction by combining multiple materials with complementary properties to achieve both strong bonding force and delamination resistance under high thermal stress conditions.
2Reliability
If the semiconductor chip is embedded in the insulating layer, then electrical performance is improved, but poor bonding force is formed between the chip and adhesive due to large CTE difference and thermal stresses
Solution Approach 1:
The patent changes the physical and chemical parameters of the chip surface by forming a five-layer metallized film with specific thicknesses (Ti: 0.5-2.0 μm, Ni: 1.0-3.0 μm, Ti: 0.5-2.0 μm, Ag: 5.0-15.0 μm, Sn: 10.0-25.0 μm). This parameter modification creates a gradient structure that gradually transitions from the chip substrate to the adhesive, reducing the CTE mismatch and thermal stress concentration at the bonding interface, thereby maintaining strong bonding force while preserving electrical performance.
Solution Approach 2:
The five-layer metallized film acts as a composite intermediate layer between the semiconductor chip and the adhesive. This composite structure with progressively different material properties (Ti for adhesion, Ni for oxidation resistance, Ag for thermal conductivity, Sn for solderability) creates a gradual transition zone that mitigates the abrupt CTE difference between the chip and adhesive, preventing bonding failure under thermal stress while maintaining electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively prevents delamination and improves the bonding force between the semiconductor chip and the adhesive, thereby enhancing the reliability of the packaging structure, particularly suitable for high-power and high-heat dissipation applications.
Implementation Method 1
due to a large difference of CTE (Coefficient of Thermal Expansion) between the semiconductor chip 10 and the adhesive 91, a poor bonding force is formed between the semiconductor chip 10 and the adhesive 91 under the effect of thermal stresses
Implementation Method 2
The metallized film usually consists of two metal layers such as titanium/silver (Ti/Ag) or three metal layers such as titanium/nickel/silver (Ti/Ni/Ag). Although the metallized film can improve the bonding force and enhance heat conduction and dissipation
Data Source
AI summary
A component-embedded packaging structure is provided, in which a plurality of metal layers are formed on an inactive surface of a semiconductor chip so as to serve as a buffer portion, and the semiconductor chip is disposed on a carrying portion with the buffer portion via an adhesive. Then, the semiconductor chip is encapsulated by an insulating layer, and a build-up circuit structure is formed on the insulating layer and electrically connected to the semiconductor chip. Therefore, the buffer portion can prevent delamination from occurring between the semiconductor chip and the adhesive on the carrying portion if the semiconductor chip has a CTE (Coefficient of Thermal Expansion) less than a CTE of the adhesive.