Chip Packaging Method With Conductive Pillars And Redistribution Structure
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Solution Overview
Problem
Current chip packaging technologies face challenges in transmitting signals between multiple chips due to insufficient line width and line pitch on circuit substrates, limiting the density and length of connection paths.
Innovation Solution
A chip packaging method involving the disposition of first chips on a carrier with conductive pillars, electrical connection of a second chip to the first chips through additional conductive pillars, encapsulation, partial removal of the encapsulant to expose pillars, and formation of a redistribution structure to enhance connection density and shorten path lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chips are mounted on a circuit substrate to form a multi-chip package structure, then signal transmission between chips is enabled, but the line width and line pitch of the circuit substrate are insufficient to meet the requirements of transmitting signals between multiple chips
Solution Approach 1:
The patent transitions from planar signal transmission on a circuit substrate to three-dimensional vertical connection through conductive pillars. Multiple chips are stacked and connected via conductive pillars extending in the vertical direction, enabling high-density signal transmission without being constrained by substrate line pitch limitations.
Solution Approach 2:
The patent introduces encapsulated material as an intermediary substance that fills the spaces between stacked chips and conductive pillars. This encapsulated material provides mechanical support, protects the conductive pillars, and enables the formation of a stable multi-chip package structure while allowing the conductive pillars to maintain precise positioning for signal transmission.
2Productivity
If conductive pillars are used to electrically connect chips in a face to face manner, then connection density increases and path lengths shorten, but the conductive pillars become exposed and require additional processing
Solution Approach 1:
The encapsulated material serves as an intermediary that simultaneously achieves multiple functions: it exposes the conductive pillars for connection while providing mechanical support and protection. This resolves the contradiction by transforming the exposed conductive pillars from a problematic state into a functional feature for high-density interconnection.
Solution Approach 2:
The patent applies partial removal of encapsulated material to selectively expose only the conductive pillars that require electrical connections, while leaving other portions of the encapsulated material intact for structural support. This localized processing approach increases connection density without requiring complete exposure of all components.
3Speed
If multiple chips are stacked and connected through conductive pillars, then signal transmission efficiency improves, but warpage and structural stability issues arise
Solution Approach 1:
The patent creates a composite structure combining multiple chips, conductive pillars, and encapsulated material. The encapsulated material acts as a matrix that binds the stacked chips and conductive pillars together, providing mechanical stability and preventing warpage while maintaining the high-speed signal transmission pathways through the conductive pillars.
Solution Approach 2:
The encapsulated material functions as an intermediary that mediates between the rigid chips and conductive pillars, providing a compliant matrix that absorbs thermal expansion differences and mechanical stresses, thereby preventing warpage while allowing the conductive pillars to maintain their precise positions for fast signal transmission.
Data Source
AI summary
A chip packaging method includes followings steps. A plurality of first chips are disposed on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are disposed on the first active surface. A second active surface of a second chip is electrically connected to the first active surfaces of the first chips through a plurality of second conductive pillars. An encapsulated material is formed, wherein the encapsulated material covers the plurality of first chips, the plurality of first conductive pillars, the second chip and the plurality of second conductive pillars. The encapsulated material is partially removed to expose each of the plurality of first conductive pillars. A redistribution structure is formed on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars.