Chip Packaging via Conductive Vias to Shorten Transmission Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional chip packaging methods, particularly wire bonding, are complex and result in long transmission paths, compromising chip performance and dimensional requirements, thus hindering the competitiveness of chip package structures.
Innovation Solution
A chip packaging method that replaces metal wires with an electrically conductive metal layer for connection between the chip and substrate, involving encapsulation, drilling through holes in the encapsulant, and plating these holes with conductive metal for direct electrical contact, allowing for simplified packaging and enhanced transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect chip and substrate, then electrical connection is established, but transmission path length increases and chip performance is compromised
Solution Approach 1:
The patent extracts and eliminates the metal wire bonding step from the packaging process. Instead of using separate wire bonds to connect chip pads to substrate pads, the invention integrates the electrical connection function directly into the substrate structure through conductive vias and trace patterns, thereby removing the source of long transmission paths
Solution Approach 2:
The patent transitions from a three-dimensional wire bonding approach (wires extending through air space) to a two-dimensional planar connection approach (conductive traces on substrate surface and vias through substrate thickness). This dimensional change dramatically shortens the transmission path while maintaining electrical connectivity
2Reliability
If wire bonding is used to connect chip and substrate, then electrical connection is established, but packaging process complexity increases
Solution Approach 1:
The patent merges the electrical connection function with the substrate structure itself. The substrate is designed with integrated conductive vias, trace patterns, and pad structures that perform both mechanical support and electrical connection functions, eliminating the need for separate wire bonding operations
Solution Approach 2:
The patent replaces the mechanical wire bonding process (requiring wire bonding equipment, tension control, and precise positioning) with a planar electrical connection system formed through standard PCB fabrication processes such as drilling, plating, and trace deposition, significantly simplifying the packaging process
3Reliability
If metal wires are used for connection, then electrical connection is achieved, but dimensional requirements of chip package structure are not met
Solution Approach 1:
The patent removes the metal wires that protrude beyond the chip package structure, eliminating the dimensional excess that prevents meeting tight dimensional requirements. The electrical connection is achieved through conductive vias and traces that remain within the substrate boundaries
Solution Approach 2:
Instead of extending connections outward from the chip through wires, the patent inverts the approach by routing connections through the substrate thickness and along its surface, keeping all connection elements contained within the substrate footprint and enabling compliance with stringent dimensional specifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the packaging process, reduces transmission path lengths, and enhances the efficiency of the chip package structure, eliminating the limitations of conventional wire bonding while allowing for efficient substrate utilization and convenient integration with printed circuit boards.
Implementation Method 1
encapsulating the chip in an encapsulant
Implementation Method 2
plating the hole wall of the first through hole as well as an area extending between the top side of the chip and the top end of the first through hole with a layer of electrically conductive metal to enable electrical connection between the chip and the substrate through the electrically conductive metal
Implementation Method 3
plating the hole wall of the first through hole as well as an area extending between the top side of the chip and the top end of the first through hole with a layer of electrically conductive metal
Data Source
AI summary
A chip packaging method begins by fixing a chip to the top side of a substrate. The chip is then encapsulated in an encapsulant. After that, the encapsulant is drilled from its top side in order to have a through hole adjacent to the chip. Lastly, an area extending between the chip and the through hole and the hole wall of the through hole are plated with an electrically conductive metal to enable electrical connection between the chip and the substrate through the electrically conductive metal. The chip packaging method solves the problems of the conventional wire bonding method, simplifies the packaging process, and provides the packaged chips with high transmission efficiency.