Chip Packaging Using Photosensitive Dielectric Layer
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Solution Overview
Problem
The existing fan-out wafer level packaging methods face challenges with chip contamination due to adhesive residue and complex process steps, particularly in forming through-holes in dielectric layers, which complicates the packaging process and reduces product yield.
Innovation Solution
A chip packaging method involving the formation of a first dielectric layer with through holes on a carrier, followed by attaching the semiconductor chip, forming a plastic encapsulation layer, separating the adhesive layer, and creating a redistribution layer based on the dielectric layer and through holes, simplifying the process and preventing contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the adhesive layer is directly attached to the chip surface, then the bonding strength is improved, but the chip is contaminated by adhesive residue
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the adhesive layer and the chip surface. This dielectric layer serves as a barrier that prevents adhesive residue from contaminating the chip while maintaining the bonding function. The dielectric layer is formed on the chip surface before applying the adhesive, creating a protective interface that eliminates contamination issues.
2Object-affected harmful factors
If a dielectric layer is formed on the adhesive layer to prevent contamination, then the chip contamination problem is solved, but the process complexity increases due to difficulty in forming through-holes
Solution Approach 1:
The dielectric layer is formed on the chip surface before the adhesive layer is applied, and through-holes are formed in the dielectric layer through-hole formation is performed in advance. This preliminary action allows for easier through-hole formation while maintaining the protective function of the dielectric layer.
3Strength
If the Si supporting wafer is used as carrier, then the chip bonding is achieved, but the process complexity increases due to difficulty in thinning and removing the Si substrate
Solution Approach 1:
The patent uses a removable carrier instead of a permanent Si supporting wafer. The carrier serves its purpose during the bonding process and then can be easily removed along with the adhesive layer, avoiding the complexity of thinning and removing Si substrate. This disposable carrier approach simplifies the overall process.
4Reliability
If bumps are fabricated on chip surface before bonding, then the electrical connection is improved, but the process complexity increases
Solution Approach 1:
The bumps are fabricated on the chip surface before the chip bonding step, as indicated in the patent. This preliminary action ensures proper electrical connection is established in advance, allowing the bonding process to proceed smoothly without additional complexity during the bonding step itself.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents chip contamination, simplifies the packaging process, and improves product yield by using a photosensitive dielectric layer as both a photoresist and dielectric material, allowing direct formation of through holes and reducing process complexity.
Implementation Method 1
using a photosensitive dielectric layer as both a photoresist and dielectric material, allowing direct formation of through holes
Data Source
AI summary
The method of chip packaging comprises: S1: providing a carrier, and forming an adhesive layer on a surface of the carrier; S2: forming a first dielectric layer on a surface of the adhesive layer, and forming a plurality of first through holes corresponding to electrical leads of a semiconductor chip in the dielectric layer; S3: attaching the semiconductor chip with the front surface facing downwards to the surface of the first dielectric layer; S4: forming a plastic encapsulation layer covering the chip on the surface of the first dielectric layer; S5: separating the adhesive layer and the first dielectric layer to remove the carrier and the adhesive layer; and S6: forming a redistribution layer for the semiconductor chip based on the first dielectric layer and the first through holes.