Chip Packaging Structure With Stress Buffer Layer for Edge Reliability
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Solution Overview
Problem
Existing chip packaging technologies fail to effectively protect the edges of chips, leading to reduced mechanical strength and reliability due to differences in thermal expansion coefficients between the encapsulant and the chip.
Innovation Solution
A chip packaging structure that includes a redistribution layer, solder balls, an encapsulant, and a stress buffer layer, where the encapsulant covers the active and back surfaces of the chip, and the stress buffer layer covers the peripheral surface, using materials like silane adhesion promoters, silicone rubber, or photosensitive dielectric materials to enhance structural strength and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If packaging materials are used to protect the edges of the chip, then chip cracking is prevented, but the difference in thermal expansion coefficient between the encapsulant and the chip leads to reduced reliability and lifespan
Solution Approach 1:
The patent introduces a stress buffer layer as an intermediary component between the chip and the encapsulant. This stress buffer layer has a thermal expansion coefficient that is intermediate between that of the chip and the encapsulant, thereby reducing the thermal stress differential and preventing reliability degradation while still providing edge protection.
Solution Approach 2:
The patent employs composite material structure by combining the encapsulant, stress buffer layer, and chip into a multi-layer composite packaging structure. Each layer is selected with specific material properties to optimize both mechanical strength and thermal expansion compatibility, resolving the contradiction between edge protection and reliability.
2Strength
If elastic materials or packaging materials are used to protect the back and spherical surface of the chip, then mechanical strength is enhanced, but the edges of the chip remain unprotected
Solution Approach 1:
The patent segments the packaging structure into distinct functional layers: the encapsulant protects the back and spherical surface while the separately introduced stress buffer layer specifically protects the edges. This segmentation allows each layer to be optimized for its specific protective function without compromising the other.
Data Source
AI summary
A chip packaging structure includes a chip, a redistribution layer, a solder ball, an encapsulant, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connected to the active surface and the back surface. The redistribution layer is disposed on the active surface of the chip. The solder ball is disposed on the redistribution layer, and the chip is electrically connected to the solder ball through the redistribution layer. The encapsulant encapsulates the active surface and the back surface of the chip, the redistribution layer, and part of the solder ball. The stress buffer layer at least covers the peripheral surface of the chip. An outer surface of the stress buffer layer is aligned with a side surface of the encapsulant.