Chip Packaging Structure With Interconnect Chip Redistribution
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Solution Overview
Problem
Conventional chip manufacturing technologies face challenges in achieving high-speed and small-volume interconnection between chips, particularly for large size integrated circuits, with existing solutions not adequately improving interconnection performance.
Innovation Solution
A packaging structure and method that includes multiple device chips with interconnection structures, a first packaging layer, a first redistribution structure electrically connected to the interconnection structure, an interconnect chip bonded to the redistribution structure, and a second packaging layer, along with micro bumps and via interconnection structures to enhance electrical connectivity between chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional chip manufacturing technologies are used for large size integrated circuits, then chip size can be increased, but interconnection performance between chips deteriorates
Solution Approach 1:
The patent divides the chip system into multiple device chips (first device chip, second device chip) that are separately manufactured and then interconnected through a substrate. This segmentation allows each chip to be optimized independently while achieving large-scale integration through the interconnection structure, resolving the contradiction between chip size and interconnection performance.
Solution Approach 2:
The patent introduces a substrate as an intermediary component that hosts multiple device chips and provides interconnection between them. The substrate acts as a mediator that enables high-performance interconnection between separate chips, allowing large-scale integration without sacrificing interconnection quality. The substrate includes interconnection structures that facilitate efficient signal transmission between chips.
2Adaptability or versatility
If smaller integrated circuits with Si bridge chips are used to achieve interconnection, then heterogeneous chip packaging is enabled, but interconnection performance still needs improvement
Solution Approach 1:
The patent creates a universal substrate structure that can accommodate different types of device chips (first device chip, second device chip with different configurations). The substrate provides a standardized interconnection platform that works with various chip types and configurations, enabling heterogeneous integration while maintaining consistent high-performance interconnection across different chip combinations.
3Reliability
If multiple packaging layers and redistribution structures are added to improve interconnection, then electrical connectivity is enhanced, but device complexity increases
Solution Approach 1:
The patent moves the interconnection functionality from the vertical dimension (multiple packaging layers stacked on top of each other) to the horizontal dimension (interconnection structures embedded within the substrate plane). The first and second redistribution structures are formed within the substrate at different horizontal levels, enabling complex electrical connectivity without requiring multiple vertical packaging layers, thus reducing overall structural complexity.
Data Source
AI summary
A packaging structure and a packaging method are provided. The packaging method includes: providing a carrier; providing a plurality of device chips, a device chip including a first side and a second side facing away from each other, and an interconnection structure being formed on the first side; attaching the plurality of device chips to the carrier, the second side of the device chip facing the carrier, forming a first packaging layer covering a side wall of the device chip and filling between the device chips on the carrier, the first packaging layer exposing the first side of the device chip; forming a first redistribution structure on the first packaging layer and the device chip; bonding an interconnect chip to the first redistribution structure; and forming a second packaging layer covering the interconnect chip on the first redistribution structure.