Chip Packaging Structure Eliminating Interposer for High-Speed Communication
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Solution Overview
Problem
Current chip packaging technologies face challenges in cost-effectiveness and structural stability due to the need for expensive through vias and interposers, particularly in 3D and 2.5D chip stacks, which also struggle with heat dissipation and warpage issues caused by material mismatch and mechanical property differences.
Innovation Solution
The development of chip packaging structures that eliminate the need for interposers with through vias by using a single-sided metal core laminate or a composite lid with a wiring layer for high-speed chip-to-chip and chip-to-carrier communication, incorporating interconnects like microbumps and tall pillar interconnects, and applying underfill materials for stability and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through vias and interposers are used in 3D and 2.5D chip stacks, then high density interconnects and electrical communications between chips are achieved, but manufacturing cost increases significantly
Solution Approach 1:
The patent removes the interposer component entirely from the chip stack architecture. Instead of using an interposer with through vias to provide interconnects, the invention directly connects chips to the substrate using bump interconnects, thereby eliminating the expensive drilling and backfilling processes while maintaining electrical communication functionality.
Solution Approach 2:
The substrate is designed to perform multiple functions: it serves as both the mechanical support structure and the interconnection medium. By integrating the interconnect functionality directly into the substrate through bump interconnects rather than requiring a separate interposer, the substrate becomes a multi-functional component that reduces overall system complexity and cost.
2Ease of manufacture
If thin, large interposers are used to reduce cost, then manufacturing cost decreases, but warpage and assembly issues increase due to material mismatch
Solution Approach 1:
By removing the interposer entirely from the architecture, the patent eliminates the source of CTE mismatch that causes warpage. The direct chip-to-substrate connection approach avoids introducing additional materials with different thermal expansion properties, thereby preventing warpage issues while still achieving cost reduction.
Solution Approach 2:
The patent employs a composite structure where chips are directly mounted on the substrate with bump interconnects, creating a more homogeneous assembly. This direct integration reduces the number of dissimilar materials in contact, minimizing thermal expansion mismatches and associated warpage problems.
3Reliability
If through holes drilling and through vias fabrication are performed in non-silicon materials such as glass, then interconnect functionality is achieved, but process difficulty and cost increase
Solution Approach 1:
The invention eliminates the need for through-hole drilling and via fabrication processes by removing the interposer structure. Instead of creating complex vertical interconnects through drilled holes in glass or other materials, the patent uses surface-mounted bump interconnects that require no drilling, significantly simplifying the manufacturing process.
Solution Approach 2:
The patent replaces the mechanical drilling and backfilling process with a deposition-based bump formation process. Instead of mechanically creating holes and filling them with metal, the invention uses electroplating or other deposition techniques to form bump interconnects directly on the substrate surface, eliminating the complex drilling and backfilling operations.
4Productivity
If 3D chip stacks with multiple layers are implemented, then chip density in two-dimensional area increases, but heat dissipation challenges increase
Solution Approach 1:
The patent segments the heat dissipation path by using thin-film thermal interface materials between each chip layer and the substrate. This segmentation allows for optimized thermal coupling at each interface, improving overall heat transfer efficiency from the chips to the substrate while maintaining high chip density.
Solution Approach 2:
The invention uses composite thermal interface materials with specific thermal conductivity properties to manage heat flow. These thin-film composite materials are designed to provide optimal thermal coupling between chips and substrate, enabling efficient heat dissipation in high-density 3D chip stacks.
Data Source
AI summary
Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip packaging structures do not require an interposer containing through silicon vias and/or provide structures having reduced warping.