Chip Packaging Structure Thickness Reduction via Layer Extraction
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Solution Overview
Problem
The existing chip packaging structures have a large thickness due to the stacking of multiple layers, which limits their application in thinner electronic products, necessitating a method to reduce the overall thickness while maintaining electrical connectivity.
Innovation Solution
A chip packaging structure comprising a conductive trace layer, an adhesion layer, and a chip, where the chip is electrically connected to the conductive trace layer, with optional features like a transfer element and encapsulation to reduce thickness and enhance functionality, and a manufacturing method involving a protection layer, conductive trace layer formation, and adhesion layer with through holes for reduced thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If multiple layers of materials are stacked to form the substrate, then the substrate provides sufficient structural support and electrical connectivity, but the overall thickness of the chip packaging structure increases
Solution Approach 1:
The patent extracts and eliminates unnecessary intermediate layers from the traditional multi-layer substrate structure. By removing redundant material layers while retaining only the essential conductive trace layer and adhesion layer, the substrate thickness is significantly reduced without compromising its structural support capability or electrical connectivity function.
Solution Approach 2:
The patent applies local quality by optimizing each remaining layer's thickness and material properties according to its specific function. The conductive trace layer is maintained at minimal necessary thickness for electrical connectivity, the adhesion layer is optimized for bonding strength, and the chip is directly mounted on the substrate surface. This localized optimization allows the overall substrate thickness to be reduced while maintaining adequate structural support where needed.
2Length of stationary object
If traditional multi-layer substrate structure is used, then electrical connectivity is ensured, but the chip packaging structure thickness cannot be reduced to desired value
Solution Approach 1:
The patent extracts and removes unnecessary intermediate insulating layers and complex multi-layer configurations from the traditional substrate structure. By retaining only the essential conductive trace layer and adhesion layer directly on the substrate, the overall thickness is reduced while electrical connectivity is maintained through the simplified but sufficient conductive path from chip pads to substrate circuit.
Solution Approach 2:
Instead of building up multiple layers to ensure connectivity, the patent inverts the approach by starting with a thin substrate and adding only the minimum necessary conductive and adhesion layers. This inverted construction methodology achieves electrical connectivity with far fewer layers, thereby reducing the overall chip packaging structure thickness to the desired value.
3Length of stationary object
If fewer layers are used to reduce thickness, then the overall structure becomes thinner, but manufacturing complexity may increase
Solution Approach 1:
The patent extracts and eliminates complex multi-layer stacking processes, alternating deposition and etching steps, and multiple alignment operations. By reducing the substrate structure to essentially a thin base layer with a conductive trace layer and adhesion layer, the manufacturing process becomes simpler and more straightforward, despite the goal of thinness.
Solution Approach 2:
The patent merges the substrate preparation, conductive trace formation, and adhesion layer deposition into a more integrated and streamlined process. By combining these steps and eliminating unnecessary intermediate processes, the manufacturing complexity is reduced even as the structure is thinned, making the simplified multi-step process more manageable than traditional complex multi-layer fabrication.
Data Source
AI summary
A method for manufacturing a chip packaging structure is disclosed. The manufacturing method includes steps of: providing a protection layer; forming a conductive trace layer on the protection layer; forming an adhesion layer on the conductive trace layer; placing a chip on the adhesion layer; and electrically connecting the chip to the conductive trace layer. Via these arrangements, the chip packaging structure made by the manufacturing method can have a smaller thickness.