Chip Packaging With Metal Frame Structure
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Solution Overview
Problem
Traditional chip packaging methods, such as wire bonding, face challenges with signal interference, noise from wire vibrations, and complexity in packaging large electric flux chips, especially in panel-level packaging where large panels and thin chips require improved efficiency and durability.
Innovation Solution
A chip packaging method involving a protective layer on the wafer surface, followed by cutting into dies, adhering these dies with a metal structure onto a carrier, and forming a molding layer, which includes metal features for connection and heat dissipation, replacing wire bonding with a simpler process that avoids signal interference and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used for chip packaging, then electrical connection is achieved, but signal interference and noise from wire vibrations occur
Solution Approach 1:
The patent replaces the mechanical wire bonding system with a metal frame structure that provides electrical connection through direct contact or proximity coupling. The metal frame acts as a rigid conductor that eliminates the vibration and signal interference problems associated with flexible wires, while maintaining electrical connectivity between the chip and external circuits.
Solution Approach 2:
The invention changes the physical state and configuration of the connection medium from flexible wires to a rigid metal frame structure. This parameter change transforms the connection method from one susceptible to vibration and interference to a stable, rigid structure that maintains consistent electrical properties and eliminates the harmful effects of wire movement.
2Reliability
If wire bonding structure is used, then electrical connection is provided, but packaging process becomes complex and not suitable for large electric flux chips
Solution Approach 1:
The patent merges the functions of electrical connection, structural support, and heat dissipation into a single metal frame structure. This consolidation eliminates the need for separate wire bonding processes and multiple components, simplifying the packaging process while maintaining electrical connection capability and improving suitability for large electric flux chips.
Solution Approach 2:
The metal frame structure serves multiple functions simultaneously: it provides electrical connection pathways, offers mechanical support for the chip, and acts as a heat dissipation structure. This multi-functionality reduces the overall complexity of the packaging system and eliminates the need for separate wire bonding and support structures.
3Productivity
If panel-level package is used, then production efficiency is improved, but warpage of large panels occurs during packaging process
Solution Approach 1:
The patent addresses panel warpage by considering thermal expansion characteristics of materials during the packaging process. The metal frame structure and molding compound are selected and designed to accommodate thermal expansion differences, reducing warpage effects during molding and subsequent thermal cycles while maintaining high production efficiency through panel-level processing.
4Reliability
If insulating layer is formed on entire panel, then electrical isolation is achieved, but process difficulty and material consumption increase
Solution Approach 1:
The patent applies electrical isolation selectively rather than uniformly across the entire panel. The metal frame structure provides localized electrical isolation where needed, while leaving other areas conductive or accessible. This local quality approach reduces the amount of insulating material required and simplifies the manufacturing process compared to forming an insulating layer on the entire panel surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances packaging efficiency, reduces signal interference and noise, and is more suitable for large electric flux chips by using metal features for connection and heat dissipation, improving the durability and applicability of the packaged chips.
Implementation Method 1
forming a protective layer on a wafer active surface of the wafer
Implementation Method 2
adhering the die and the metal structure onto a carrier
Implementation Method 3
forming a molding layer
Data Source
AI summary
The present disclosure provides a chip packaging method and a chip structure. The chip packaging method comprises: providing a wafer, and forming a protective layer on a wafer active surface of the wafer; cutting and separating the wafer to form a die; providing a metal structure, the metal structure including at least one metal unit; adhering the die and the metal structure onto a carrier; and forming a molding layer. The chip structure comprises: at least one die; a protective layer; a metal unit, the metal unit including at least one metal feature; and a molding layer, encapsulating the at least one die and the metal unit, and the chip structure is connected with an external circuit through the at least one metal feature. By adopting a plurality of metal features of the metal unit, the present disclosure achieves improved packaging performance brought by different metal features; and the wafer active surface is provided with the protective layer in the present disclosure, so that a step of applying an insulating layer after the formation of the molding layer is omitted.