Chip Packaging Overflow Proof Device with Retaining Wall
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packaging processes face issues with colloid squeeze-out due to excessive filling or high viscosity, leading to compromised appearance and increased costs for removal, as well as potential impact on binding strength between the colloid and packaging base.
Innovation Solution
A packaging base with an overflow space is designed to accommodate squeeze-out, featuring a retaining wall and a second cable-terminating hole positioned lower than the first, allowing any excess colloid to enter the overflow space without escaping the packaging base, thus preventing damage and maintaining appearance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If packaging colloid is filled excessively or with high viscosity, then the chip is well protected, but colloid squeeze-out occurs compromising appearance and binding strength
Solution Approach 1:
The packaging base is segmented into functional zones: a normal filling space for chip protection and an overflow space for containing excess colloid. The retaining wall creates this segmentation, directing squeeze-out into the overflow space rather than allowing it to compromise the appearance or binding strength of the main packaging structure.
Solution Approach 2:
The harmful effect of colloid squeeze-out is converted into a beneficial feature by designing the overflow space to intentionally receive and contain the excess colloid. What was previously a defect (squeeze-out) becomes a controlled feature that maintains both chip protection and appearance quality.
2Reliability
If colloid squeeze-out occurs, then chip protection is maintained, but appearance is compromised and extra removal cost is incurred
Solution Approach 1:
The overflow space converts the harmful squeeze-out into a beneficial containment feature. Excess colloid is directed into the overflow space during filling, eliminating the need for post-filling removal processes and associated costs while maintaining chip protection.
Solution Approach 2:
The overflow space is pre-designed and positioned during the packaging base manufacturing stage. This preliminary action prevents squeeze-out issues before they occur during the colloid filling process, eliminating the need for costly post-processing removal operations.
3Reliability
If colloid squeeze-out occurs, then chip protection is maintained, but binding strength between colloid and packaging base is affected
Solution Approach 1:
The packaging base is divided into a binding area (normal filling space) and an overflow area separated by the retaining wall. This segmentation ensures that excess colloid is contained in the overflow space away from critical bonding regions, preserving the binding strength between the colloid and packaging base while maintaining chip protection.
4Object-affected harmful factors
If retaining wall is added to create overflow space, then colloid squeeze-out is prevented, but device complexity increases
Solution Approach 1:
The retaining wall is a localized structural feature added only in specific areas of the packaging base where overflow control is needed. This local modification rather than a complete structural redesign minimizes the increase in device complexity while effectively preventing colloid squeeze-out.
Data Source
AI summary
A chip packaging overflow proof device includes a chip disposed on a substrate; a circuit connected to the chip being provided to each of both sides of the substrate; both of the substrate and the chip being placed in a packaging base; a socket being each provided on both sides of the packaging base to receive insertion by a lid; a first cable-terminating hole being provided between the socket and the lid to permit the circuit to penetrate through; one or a plurality of retaining wall being disposed on the packaging base at where closer to the socket; a second cable-terminating hole being provided on the retaining hole; an overflow space being defined between the retaining wall and the socket; the overflow space being disposed at a level lower than that of the second cable-terminating hole; and the overflow space accepts any squeeze-out from a chip packaging colloid.


