Chip Packaging Structure With Passivation Groove for Stable Encapsulation
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Solution Overview
Problem
Conventional chip packaging methods face issues with chip displacement during encapsulation due to poor bonding forces between the encapsulation layer and dielectric layer, leading to reliability concerns and defective products.
Innovation Solution
A chip packaging structure with a passivation layer and encapsulation layer design that enhances bonding force through a via hole connection and a groove on the passivation layer, along with a conductive reinforcement layer and back side protection layers to stabilize the chip and prevent stress extension.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the trench is formed by dry etching method to divide the wafer into individual chips, then the chip separation is achieved, but the passivation layer is completely etched causing poor chip fixation
Solution Approach 1:
The patent applies local quality by forming a groove around the circumference of the passivation layer rather than completely etching it. This localized modification preserves the passivation layer's structural integrity for chip fixation while still enabling chip separation through the groove, resolving the contradiction between ease of manufacture and reliability.
2Strength
If the encapsulation layer is joined to the dielectric layer, then the bonding is achieved, but water absorption and poor wettability cause delamination
Solution Approach 1:
The patent introduces the passivation layer as an intermediary between the encapsulation layer and the dielectric layer. The passivation layer with its groove structure serves as a mediator that improves bonding stability by preventing direct contact between the encapsulation layer and water-absorbing dielectric layer, while still maintaining the bonding force through the groove interface.
3Ease of operation
If the passivation layer is completely etched to expose the dielectric layer, then the chip can be accessed, but the chip cannot be well fixed and may be displaced
Solution Approach 1:
The patent applies local quality by creating a groove around the circumference of the passivation layer instead of completely etching it. This localized approach maintains the passivation layer's presence for chip fixation and alignment precision while still providing access to the chip through the groove, resolving the contradiction between ease of operation and manufacturing precision.
Data Source
AI summary
The present invention provides a chip packaging structure and a chip packaging method. Compared with an existing method of joining an encapsulation layer with a dielectric layer, adhesion between the encapsulation layer and a chip in the present invention is increased, and the encapsulation layer is less likely to fall off under stress. Furthermore, during the packaging process, a passivation layer enables chips to be mutually fixed together, which can prevent the chips from being shifted during the encapsulation process, and thereby enhance the reliability of the final product and improve the yield of the final product.