Chip Packaging Structure With Segmented Signal Leads
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Solution Overview
Problem
Conventional chip packaging structures, particularly in the COF process, face issues with lead breakage due to increased stress when flexible substrates are bent, as the distance between conducting points decreases, leading to reduced durability and reliability.
Innovation Solution
The proposed chip packaging structure optimizes lead distribution by reducing the width and space occupied by non-signal leads, allowing for a wider and more robust signal lead configuration, with signal leads extending beyond a second boundary and incorporating turning parts for enhanced flexibility and endurance, while an insulating layer covers the leads to further enhance structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of conducting points is increased to achieve higher pin count, then the functionality and connectivity of the chip packaging structure is improved, but the distance between conducting points becomes smaller resulting in narrower leads that break more easily under stress
Solution Approach 1:
The lead structure is segmented into different width portions: a first width portion closer to the chip with narrower width, and a second width portion farther from the chip with wider width. This segmentation allows the lead to accommodate high pin count while maintaining durability through the wider second portion that resists stress and breakage.
Solution Approach 2:
Different portions of the lead are given different local qualities in terms of width. The first width portion has narrower width to accommodate dense conducting points, while the second width portion has wider width to provide mechanical strength and bend endurance. This local quality variation resolves the contradiction between high pin count and lead durability.
2Adaptability or versatility
If non-signal leads are used to occupy space for future expansion, then the adaptability and versatility of the packaging structure is improved, but the available space for signal leads is reduced resulting in narrower signal leads with poorer bend endurance
Solution Approach 1:
Instead of reserving space for future expansion (preliminary action), the invention takes the opposite approach by making signal leads wider now to ensure current reliability. The patent prioritizes present signal lead performance over future expansion capability, resolving the contradiction by choosing reliability as the primary concern.
Solution Approach 2:
The conventional approach reserves space for future expansion, but this invention inverts the approach by allocating maximum space to current signal leads. Rather than preparing for future needs, the design optimizes for present signal lead durability, making signal leads wider than conventional designs would allow.
3Reliability
If signal leads are made wider to improve bend endurance, then the reliability and durability of the packaging structure is improved, but the space required for lead distribution increases resulting in larger overall package size
Solution Approach 1:
The lead width is segmented into two portions: a narrower first width portion and a wider second width portion. This segmentation allows the lead to have sufficient bend endurance in the wider second portion while minimizing the overall area occupied by the narrower first portion, thus resolving the contradiction between reliability and package size.
Solution Approach 2:
The lead structure employs local quality variation with different widths at different locations. The wider second width portion provides the necessary bend endurance and reliability, while the narrower first width portion reduces the overall area consumption. This localized optimization resolves the contradiction between improving reliability and minimizing package area.
Data Source
AI summary
A chip packaging structure includes a flexible plate, a chip, and a plurality of leads. The chip is disposed on the flexible plate. A first boundary and a second boundary are defined on the flexible plate. The first boundary is located between the chip and the second boundary. A first area is formed between the first boundary and the chip. A second area is formed between the first boundary and the second boundary. The chip includes a plurality of signal conducting points and a plurality of non-signal conducting points. The plurality of leads are disposed on the flexible plate and include a plurality of signal leads and a plurality of non-signal leads. The width of the non-signal lead is smaller than the width of the signal lead extending out of the second boundary.