3D Chip Packaging Thermal Management via Segmented Heat Conductors
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Solution Overview
Problem
Advanced packaging technologies for high-bandwidth memory devices face limitations in I/O speed, power consumption, high costs due to TSV processes, complex silicon bridge and redistribution layer processes, and heat dissipation issues in 3D packaging.
Innovation Solution
A packaging structure that includes a first and second chip with heat-conducting surfaces, connected by first and second heat conductors to enhance heat dissipation, with optional features such as substrates with cavities and interposers to improve thermal conductivity and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 3D packaging is applied to active devices, then integration density is improved, but heat dissipation capability deteriorates
Solution Approach 1:
The patent divides the heat dissipation function into multiple independent heat conductors (first heat conductor and second heat conductor) that are separately connected to different chips (first chip and second chip). This segmentation allows heat from each chip to be dissipated through dedicated pathways, preventing heat accumulation and improving overall heat dissipation capability while maintaining 3D packaging integration density.
Solution Approach 2:
The patent introduces heat conductors as intermediary components between the chips and the external environment. These heat conductors act as thermal mediators that efficiently transfer heat away from the chips, resolving the heat dissipation problem inherent in 3D packaging without compromising integration density.
2Reliability
If interposer and silicon bridge are used for connection, then electrical connectivity is improved, but I/O speed is limited and power consumption increases
Solution Approach 1:
The patent extracts and eliminates the interposer and silicon bridge components from the packaging structure. By directly connecting chips through bonding pads and conductive structures, the design removes the thermal and electrical bottlenecks introduced by these intermediary components, thereby improving I/O speed and reducing power consumption while maintaining reliable electrical connectivity.
Solution Approach 2:
The patent transitions from a planar 2D connection architecture (using interposers and silicon bridges) to a vertical 3D stacking architecture. This dimensional change enables direct chip-to-chip connections through the thickness direction, shortening signal paths and improving I/O speed while reducing the need for complex intermediary structures.
3Productivity
If TSV process is used for 2.5D packaging, then interconnection density is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive TSV (Through-Silicon Via) processes with more cost-effective bonding and conductive structure techniques. By using readily available materials and simpler fabrication steps such as direct bonding and conductive paste application, the design achieves comparable interconnection density without the high manufacturing costs associated with TSV processes.
4Adaptability or versatility
If RDL redistribution is implemented, then wiring flexibility is improved, but wiring density is limited
Solution Approach 1:
The patent moves the interconnection architecture from a 2D planar RDL (Redistribution Layer) structure to a 3D vertical stacking structure. This dimensional transition enables much higher wiring density by utilizing the vertical dimension for signal routing, while still maintaining wiring flexibility through the modular chip stacking architecture and configurable bonding pad arrangements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly improves heat dissipation efficiency by forming heat-conducting channels between the chips and heat conductors, addressing the limitations of existing technologies in high-bandwidth memory packaging.
Implementation Method 1
a first heat conductor and a second heat conductor, the first heat conductor being connected to the first heat-conducting surface, and the second heat conductor being connected to the second heat-conducting surface
Data Source
AI summary
The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a first chip, a second chip, a first heat conductor and a second heat conductor, wherein the first chip includes a first connecting surface and a first heat-conducting surface; the second chip is disposed on a side of the first connecting surface and electrically connected to the first chip, and a side of the second chip distal from the first chip includes a second heat-conducting surface; the first heat conductor is connected to the first heat-conducting surface; and the second heat conductor is connected to the second heat-conducting surface. A first heat-conducting channel is formed between the first heat-conducting surface and the first heat conductor, a second heat-conducting channel is formed between the second heat-conducting surface and the second heat conductor. Thus, the heat dissipation efficiency of the packaging structure can be significantly improved.