Chip Packaging Structure With TSV-Over-Pad Layout
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Solution Overview
Problem
Conventional chip packaging methods face challenges in reducing the size of semiconductor devices while maintaining circuit performance, as the arrangement of copper pillars and through silicon vias (TSVs) occupies space in the functional circuit region, leading to potential short circuits and performance issues.
Innovation Solution
A chip packaging method where a passivation layer is applied on the pads of the wafer, followed by the formation of bonding layers on the substrate, allowing TSVs to be positioned above the pads without occupying the bonding layer area, thus increasing the functional circuit region's area and ensuring performance even with reduced chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper pillars and TSVs are arranged in the functional circuit region to connect circuits, then signal transmission is achieved, but the area of the functional circuit region is reduced
Solution Approach 1:
The invention moves the TSV arrangement from the functional circuit region to the pad region, utilizing the vertical dimension above the pads. This dimensional relocation allows TSVs to connect circuits without occupying horizontal space in the functional circuit region, thus resolving the area reduction problem while maintaining signal transmission capability.
Solution Approach 2:
The invention introduces passivation layers as intermediaries between the pads and the bonding layers. These passivation layers enable the pads to serve dual purposes: as bonding interfaces and as support structures for TSVs, eliminating the need for separate copper pillars and freeing up functional circuit region area.
2Volume of moving object
If chip size is reduced to decrease device volume, then device compactness is improved, but circuit performance deteriorates
Solution Approach 1:
By relocating TSVs to the pad region and utilizing the vertical space above pads, the invention enables chip area reduction without compromising functional circuit region area. This allows smaller chip volume while maintaining circuit performance through preserved functional area.
Solution Approach 2:
The pads are designed to serve multiple functions: as bonding interfaces, as support structures for TSVs, and as electrical connections. This multi-functionality eliminates the need for separate copper pillars, allowing area reduction while maintaining circuit performance.
3Device complexity
If pads serve as bonding layers directly, then bonding process is simplified, but TSV arrangement occupies bonding layer area
Solution Approach 1:
The invention introduces passivation layers as intermediaries between the pads and bonding layers. This layered structure allows pads to maintain their bonding function while providing vertical space for TSV arrangement, preventing TSVs from occupying bonding layer area and maintaining clear bonding interfaces.
Solution Approach 2:
The invention segments the pad structure by adding separate passivation layers, creating distinct functional zones: the pad for electrical connection, the passivation layer for insulation and TSV support, and the bonding layer for mechanical bonding. This segmentation resolves the area conflict while maintaining bonding simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the area utilization of the functional circuit region, improves bonding reliability with metal bonding, and maintains circuit performance as the chip size decreases, reducing the risk of short circuits and ensuring effective signal transmission.
Implementation Method 1
bonding the first bonding layer and the second bonding layer, so that the third surface and a surface of the passivation layer away from the wafer are attached together
Data Source
Figure 1
Figure 2
Figure 3~6
AI summary
Provided are a chip packaging method and a chip packaging structure. The passivation layer is arranged on the pads of the wafer, then the first bonding layer is formed on the passivation layer, and the second bonding layer is formed on the substrate. The substrate and the wafer are bonded and packaged together by bonding the first bonding layer and the second bonding layer. The pads are only used as a conductive structure, not as a bonding layer due to the passivation layer arranged between the pads and the bonding layer. The through silicon via is arranged at the position above the pad and avoiding the bonding layer, so as to connect the functional circuit region between the wafer and the substrate to the outside of the chip packaging structure.