Protective-Layer Chip Packaging for Warpage and Die Alignment
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Solution Overview
Problem
The panel-level packaging process faces challenges such as warpage, accuracy of die alignment, and difficulties in packaging small and thin chips due to the limitations of traditional large panel packaging techniques, especially in the context of emerging trends towards smaller and lighter electronic devices.
Innovation Solution
A chip packaging method involving the formation of a protective layer with specific mechanical and thermal properties on the die active surface, including an organic/inorganic composite material with filler particles, to provide buffering, support, and prevent burring and chipping during singulation, while ensuring alignment and stability during encapsulation and conductive layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional large panel packaging technique is used, then production efficiency is improved, but warpage and alignment accuracy deteriorate
Solution Approach 1:
The patent segments the large panel into multiple smaller sub-panels or processing zones. Each sub-panel can be processed and handled independently, reducing the overall size and weight that causes warpage while maintaining the benefits of panel-level packaging for production efficiency.
2Ease of manufacture
If panel-level packaging is used, then production costs are reduced, but difficulties in packaging small and thin chips increase
Solution Approach 1:
The patent applies local quality by providing enhanced support and protection specifically at critical locations where small and thin chips are vulnerable, such as at the edges and corners of the panel, while maintaining cost-effective panel-level processing for the overall structure.
3Length of moving object
If die thickness is reduced for smaller devices, then device size is reduced, but susceptibility to burring and chipping increases
Solution Approach 1:
The patent applies beforehand cushioning by providing protective layers, support structures, or cushioning materials before the singulation process to prevent burring and chipping of thin dies. This pre-protection allows thinning of dies for smaller devices while maintaining their strength during processing.
4Strength
If protective layer with filler particles is used, then buffering and support are improved, but manufacturing complexity increases
Solution Approach 1:
The patent uses composite materials by incorporating filler particles into the protective layer to enhance its mechanical properties such as buffering and support capabilities. This composite approach provides improved strength while managing manufacturing complexity through established composite material processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces warpage, improves die alignment accuracy, and enhances the durability of packaged chips, making it suitable for large panel-level and thin chip packaging with high electric flux applications.
Implementation Method 1
the protective layer includes Young's Modules and a protective layer thickness for providing buffering and support for a conductive layer and for preventing burring and chipping from a singulation process
Implementation Method 2
the protective layer includes a coefficient of thermal expansion for preventing interface stress and interface fatigue between the dies and the protective layer
Data Source
AI summary
The present disclosure provides a chip packaging method and a package structure. The chip packaging method comprises: forming a protective layer having material properties on a die active surface of a die; attaching (such as adhering) the die in which the die active surface is formed with the protective layer onto a carrier, the die active surface facing the carrier, and a die back surface of the die facing away from the carrier; forming an encapsulation layer having material properties to encapsulate the die; removing (such as stripping off) the carrier to expose the protective layer; and forming a conductive layer and a dielectric layer. The chip packaging method reduces or eliminates warpage in the panel packaging process, lowers a requirement on an accuracy of aligning the die on the panel, reduces a difficulty in the panel packaging process, and makes the packaged chip structure more durable, and thus the present disclosure is especially suitable for large panel-level package and package of a thin chip with a large electric flux.