Chip Pad Barrier Layer Layout Against Chloride Corrosion
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Solution Overview
Problem
There is a need to enhance the structural reliability between the chip pad and the redistribution via pattern in semiconductor packages, as chloride ions in the redistribution dielectric layer can permeate the chip pad, leading to corrosion and reduced reliability.
Innovation Solution
A semiconductor package design that includes a barrier layer with separate openings for the connection and test portions of the chip pad, where the connection portion is surrounded by the barrier layer and not in direct contact with the redistribution dielectric layer, preventing chloride ion permeation and enhancing structural reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the chip pad is in direct contact with the redistribution dielectric layer, then the manufacturing process is simplified, but chloride ions can permeate the chip pad causing corrosion and reducing structural reliability
Solution Approach 1:
The chip pad surface is segmented into multiple portions: a connection portion surrounded by the barrier layer and not in direct contact with the redistribution dielectric layer, and a test portion in direct contact with the redistribution dielectric layer. This segmentation allows the connection portion to be protected from chloride ion permeation while maintaining manufacturing simplicity.
Solution Approach 2:
The barrier layer acts as an intermediary between the chip pad and the redistribution dielectric layer. It defines a first opening that exposes the connection portion to the redistribution via pattern while preventing direct contact between the connection portion and the redistribution dielectric layer, thus blocking chloride ion permeation pathways.
2Reliability
If the connection portion is surrounded by the barrier layer, then chloride ion permeation is prevented, but the manufacturing precision requirement increases
Solution Approach 1:
The barrier layer is segmented to define separate openings: a first opening for the connection portion and a second opening for the test portion. The first opening is positioned to expose the connection portion while being surrounded by the barrier layer, creating a controlled exposure zone that balances protection requirements with manufacturing feasibility.
Solution Approach 2:
Different portions of the chip pad receive different treatments: the connection portion is locally protected by being surrounded by the barrier layer and exposed only through the first opening, while the test portion remains in direct contact with the redistribution dielectric layer through the second opening. This local quality differentiation optimizes both corrosion resistance and manufacturability.
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes a chip pad of a semiconductor chip, the chip pad including a connection portion and a test portion in a first surface of the chip pad; a barrier layer covering the chip pad, the barrier layer defining a first opening and a second opening that is separate from the first opening, the first opening exposing the connection portion of the chip pad, and the second opening exposing the test portion of the chip pad; and a redistribution structure.