Semiconductor Chip Pad Configuration Optimization
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Solution Overview
Problem
Existing integrated circuit (IC) chip pad configurations result in significant wastage of silicon area due to sparse pin distribution, leading to inefficient use of chip pad rings, especially in chips with fewer pins.
Innovation Solution
A method to optimize semiconductor chip pad configuration by determining dimensions x and y based on the number of pins and chip core length, allowing for a horizontally configured pin area instead of a vertically configured one, with ESD cells and circuits designed to fit within these dimensions, minimizing wasted area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If pad length L is kept as long as possible to facilitate access during IC fabrication and packaging, then ease of manufacture is improved, but chip area utilization deteriorates due to wasted silicon area
Solution Approach 1:
The patent changes the pad dimensional parameters from traditional long rectangular shapes to optimized dimensions where length L is approximately 1/6 of chip core length and width W is approximately 1/6 of chip core width. This parameter optimization reduces the pad area while maintaining manufacturing accessibility, directly resolving the contradiction between ease of manufacture and chip area utilization.
Solution Approach 2:
The patent reorients the pin longitudinal axis to be parallel to the chip core rather than perpendicular, and positions pads at corners and midpoints of chip sides. This dimensional reconfiguration allows shorter pad lengths while maintaining access during fabrication, reducing wasted area without compromising manufacturing ease.
2Device complexity
If pads are spaced sparsely in chip pad ring to accommodate fewer pins, then device complexity is reduced, but chip area utilization deteriorates due to large wasted portions
Solution Approach 1:
The patent segments the chip pad ring into specific positions: corners and midpoints of each side. For N pins per side, pads are placed at corner positions and intermediate positions calculated as (Lc/(2*N)) spacing. This segmentation allows efficient packing of pads with reduced spacing while maintaining organized structure, improving area utilization without excessive complexity.
Solution Approach 2:
The patent uses partial action by placing pads only at corner and midpoint positions rather than uniformly distributing them. This selective placement optimizes area utilization for chips with fewer pins, using exactly the number of pads needed (4 corners + 4*N intermediate positions) without unnecessary complexity.
3Reliability
If ESD cells are made long to protect the pad, then reliability is improved, but chip area utilization deteriorates due to increased pad length requirement
Solution Approach 1:
The patent optimizes ESD cell dimensions to be approximately 1/16 of chip core length and 1/16 of chip core width, significantly shorter than traditional long ESD cells. This parameter change maintains ESD protection reliability while reducing the area occupied by ESD cells, resolving the contradiction between reliability and chip area utilization.
Data Source
AI summary
An optimized semiconductor chip pad configuration. The pad includes a pad circuit area Ap, a first dimension x and a second dimension y, in a chip having N number of pins on each side. The pins include a longitudinal axis, and the chip includes a chip core of length Lc. The method includes determining the first dimension x by dividing the length Lc by the N, determining the second dimension y by dividing the pad circuit area Ap by a result of a division of the length Lc by the N, and creating a semiconductor area pad that includes pins with the longitudinal axis positioned parallel to the chip core. A stack of circuits is designed in the chip to fit in the pad based on the first dimension x and the second dimension y.