Semiconductor Chip Pad Layout for Thin Package Reliability
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Solution Overview
Problem
The challenge is to reduce the thickness of semiconductor chips while maintaining reliability, particularly in stacked semiconductor packages where parasitic capacitance and RC delay issues arise due to the integration of multiple layers and the need for test pads.
Innovation Solution
A semiconductor chip design featuring a semiconductor substrate with an integrated device layer, a multi-wiring layer, and a pad metal layer with test pads, where the pad metal layers are structured such that the central portion is exposed and the outer portion overlaps the wires, preventing wire overlap with test pads and reducing the risk of cracks during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the chip thickness is reduced to meet miniaturization demands, then the chip size and weight are reduced, but the reliability deteriorates due to increased stress on wires and potential cracks during testing
Solution Approach 1:
The pad metal layer is segmented into two distinct functional zones: a central portion that is exposed for test pad functionality and an outer portion that overlaps with wires for structural support. This segmentation allows each zone to optimize its specific function while working together to resolve the contradiction between thinness and reliability.
Solution Approach 2:
Different regions of the pad metal layer are given different properties: the central portion is exposed to provide electrical contact for testing, while the outer portion maintains overlap with wires to provide mechanical strength. This local differentiation of properties allows the same layer to simultaneously enable thin chip design and prevent wire cracks.
2Ease of operation
If test pads are included for semiconductor chip testing, then testing capability is improved, but the chip complexity increases due to additional pad metal layers and structures
Solution Approach 1:
The pad metal layer serves multiple functions simultaneously: it provides structural support to prevent wire cracks, enables electrical contact for testing through the exposed central portion, and maintains electrical connectivity through the outer portion that overlaps with wires. This multi-functionality reduces the need for separate dedicated structures for each function.
Solution Approach 2:
The structural support function and test pad function are merged into a single pad metal layer rather than using separate layers. The central portion is exposed for testing while the outer portion provides structural overlap, combining two functions that could have been implemented separately into one integrated structure.
3Adaptability or versatility
If multiple layers of wires are integrated to increase functionality, then the chip capability is improved, but parasitic capacitance increases causing RC delay
Solution Approach 1:
Instead of adding more wire layers in the vertical dimension which increases parasitic capacitance, the pad metal layer extends in the horizontal plane with its outer portion overlapping wires laterally. This dimensional approach provides additional connectivity and structural support without stacking more conductive layers that would increase RC delay.
Data Source
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AI summary
Provided are a semiconductor chip with a reduced thickness and improved reliability, and a semiconductor package including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, an integrated device layer on the semiconductor substrate, a multi-wiring layer on the integrated device layer, and a pad metal layer of a plurality of pad metal layers on the multi-wiring layer, and having test pads defined therein. The pad metal layers extend in a first direction parallel to a top surface of the semiconductor substrate or in a second direction perpendicular to the first direction. A test pad is a central portion of the pad metal layer and, and an outer portion of the pad metal layer excluding the test pad overlaps the wires in a third direction perpendicular to the top surface of the semiconductor substrate.