Semiconductor Chip Pad Layout for Parallel Switching Stability
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Solution Overview
Problem
Conventional semiconductor circuit devices face challenges in maintaining uniform resistance and reactance components between electrode pads of the same type when multiple semiconductor chips are connected in parallel, leading to oscillations in current and voltage waveforms during turn OFF, which can result in erroneous operation or device destruction.
Innovation Solution
The semiconductor circuit device employs a configuration where multiple semiconductor chips with different electrode pad layouts are mounted on a substrate, with electrode pads of the same type connected in parallel through metal members. The layouts of the electrode pads on each chip are designed to ensure that the resistance and reactance components between pads connected in parallel are uniform, thereby minimizing oscillations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple semiconductor chips are connected in parallel to increase current capacity, then the current handling capability is improved, but the uniformity of resistance and reactance components between electrode pads deteriorates, causing oscillations in current and voltage waveforms
Solution Approach 1:
The patent applies asymmetry by intentionally designing different electrode pad layouts for different semiconductor chips. Specifically, chips are arranged with different orientations (e.g., 0 degrees, 90 degrees, 180 degrees, 270 degrees) and different pad configurations relative to their connection points. This asymmetric arrangement compensates for the inherent differences in parasitic inductance and resistance, making the total impedance seen by each parallel-connected device as uniform as possible, thereby suppressing waveform oscillations during turn-off transitions.
2Device complexity
If conventional electrode pad layouts are used without optimization, then the device structure is simple, but oscillations occur in current and voltage waveforms during turn OFF, leading to erroneous operation or device destruction
Solution Approach 1:
The patent applies parameter changes by systematically varying the electrode pad layout parameters across different semiconductor chips. This includes changing the position, orientation, and configuration of pads relative to the connection points on the substrate. By optimizing these geometric parameters, the parasitic inductance and resistance values are adjusted to achieve uniform impedance characteristics across all parallel-connected devices, thereby eliminating harmful oscillations during switching operations.
Data Source
AI summary
A layout of electrode pads on a front surface of a first semiconductor chip is different from a layout of them on a second semiconductor chip. An overall layout of the semiconductor chips mounted on the insulated substrate and the layouts of the electrode pads on the front surfaces of the semiconductor chips including the first and second semiconductor chips are determined so that a value of a resistance component and/or a value of a reactance component between each two electrode pads that are the same type respectively on different semiconductor chips and are connected in parallel become the same. As a result, current waveform oscillation between semiconductor devices fabricated on the semiconductor chips, respectively, may be suppressed.