Chip Pad Leveling With Heat and Pressure for Fine-Pitch Bonding
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Solution Overview
Problem
The existing technologies for chip bonding on circuit substrates face inefficiencies due to the limited size of solder balls, which cannot effectively connect chips with small pad sizes or spacings, leading to inadequate utilization of layout space and poor electrical connections.
Innovation Solution
A chip pad surface leveling device comprising a signal control module, a glass carrying module, and a temperature control module, which levels the bonding pad ends of convex pillar structures on chips by applying a predetermined pressure and temperature through a leveling glass substrate, ensuring a surface roughness of less than 1 μm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If solder balls are used for electrical connection between chip and circuit substrate, then electrical connection is achieved, but the minimum pad size and spacing are limited by the predetermined reduction limit of solder ball size
Solution Approach 1:
The invention changes the physical state and properties of the bonding material from solid solder balls to a material that undergoes phase change (solid-liquid-solid) during bonding. This allows the bonding material to adapt to smaller pad sizes and spacings while maintaining reliable electrical connection, as the material can flow and conform to the exact pad geometry during the molten state.
Solution Approach 2:
The invention replaces the mechanical placement of pre-formed solder balls with a system that delivers bonding material in a controlled manner (e.g., through printing or dispensing). This substitution allows for more precise control of material placement and enables smaller pad dimensions while ensuring complete coverage and reliable electrical connection.
2Productivity
If heterogeneous chips are individually arranged on circuit substrate, then chip functionality is achieved, but layout space utilization is poor
Solution Approach 1:
The invention merges multiple heterogeneous chips into a stacked three-dimensional configuration rather than arranging them individually on the substrate plane. This vertical integration dramatically improves layout space utilization by stacking chips above each other, allowing multiple functional layers to occupy the same footprint area while maintaining electrical connections through through-silicon vias and bonding interfaces.
Solution Approach 2:
The invention transitions from two-dimensional planar arrangement of chips to three-dimensional vertical stacking. By utilizing the vertical dimension, the system achieves much higher density and space utilization, as chips are arranged in multiple layers along the Z-axis rather than being confined to a single plane, thereby improving overall layout efficiency.
3Manufacturing precision
If solder ball size is reduced to accommodate smaller pad sizes, then pad size limitation is addressed, but the reduction limit is predetermined and cannot be further reduced
Solution Approach 1:
The invention replaces the mechanical fabrication and placement of solder balls with a material deposition system that can deliver bonding material directly to the pad area in controlled amounts. This substitution eliminates the predetermined reduction limit of solder ball fabrication, as the material can be deposited in any required quantity and configuration, enabling continuous scaling to smaller pad sizes without hitting manufacturing roadblocks.
Solution Approach 2:
The invention changes the delivery mechanism and physical state of the bonding material, allowing it to be supplied in a form that can be precisely controlled during application. This enables the bonding material to be delivered in quantities suitable for very small pad sizes while maintaining ease of manufacture, as the material properties (viscosity, flow characteristics) can be adjusted to match the required pad dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device effectively levels the bonding pad ends of chips, enabling efficient electrical connections without the need for pre-prepared solder balls, thereby optimizing chip placement and layout utilization.
Implementation Method 1
the temperature control module being configured to apply a predetermined temperature to the first convex pillar structures of the first chip or the second convex pillar structures of the second chip
Implementation Method 2
the glass carrying module being configured to apply a predetermined pressure to the first convex pillar structures of the first chip or the second convex pillar structures of the second chip through the leveling glass substrate
Data Source
AI summary
A chip pad surface leveling device includes a signal control module, a glass carrying module and a temperature control module. The glass carrying module is configured to move a leveling glass substrate to contact a plurality of first convex pillar structures of a first chip or a plurality of second convex pillar structures of a second chip. The temperature control module is configured to apply a predetermined temperature to the first convex pillar structures or the second convex pillar structures, and the glass carrying module is configured to apply a predetermined pressure to the first convex pillar structures or the second convex pillar structures through the leveling glass substrate, thereby making a surface roughness of a bonding pad end of each first convex pillar structure or a surface roughness of a bonding pad end of each second convex pillar structure is not greater than 1 μm.